Browse Prior Art Database

Skewed Placement of Chips for Reduced Interconnection Length

IP.com Disclosure Number: IPCOM000112700D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Daniels, L: AUTHOR [+4]

Abstract

Conventional placement of integrated circuit chips on chip carriers is centered as illustrated in Fig. 1. Disclosed here is the concept of non-central chip placement as shown in Fig. 2. Custom placement of chips on their carriers and of these carriers on the second level assembly will reduce the length of printed wiring necessary to interconnect the chips. This concept would be selectively applied to critical circuits requiring the shortest circuit-to-circuit time delay.

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Skewed Placement of Chips for Reduced Interconnection Length

      Conventional placement of integrated circuit chips on chip
carriers is centered as illustrated in Fig. 1.  Disclosed here is the
concept of non-central chip placement as shown in Fig. 2.  Custom
placement of chips on their carriers and of these carriers on the
second level assembly will reduce the length of printed wiring
necessary to interconnect the chips.  This concept would be
selectively applied to critical circuits requiring the shortest
circuit-to-circuit time delay.