Browse Prior Art Database

Application of Selftest with Error Isolation

IP.com Disclosure Number: IPCOM000112704D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Hansen, MW: AUTHOR [+2]

Abstract

The Bug Isolation Tool combines the concept of generating pseudorandom patterns to scan into a chip for testing while providing a way to isolate failures without deterministic patterns. After the patterns are scanned into the chip under test, the chip is put into a mode that allows these patterns to be propagated through the chip's combinatorial logic with the system clocks at full system speed. The resulting patterns are then scanned out of the chip and into a signature register. This signature register is then checked after a given number of cycles to determine if a fail has occurred. When a fail does occur, this tool uses a novel combination of the pseudorandom patterns and some compare circuitry to isolate the latch that caused the fail.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Application of Selftest with Error Isolation

      The Bug Isolation Tool combines the concept of generating
pseudorandom patterns to scan into a chip for testing while providing
a way to isolate failures without deterministic patterns.  After the
patterns are scanned into the chip under test, the chip is put into a
mode that allows these patterns to be propagated through the chip's
combinatorial logic with the system clocks at full system speed.  The
resulting patterns are then scanned out of the chip and into a
signature register.  This signature register is then checked after a
given number of cycles to determine if a fail has occurred.  When a
fail does occur, this tool uses a novel combination of the
pseudorandom patterns and some compare circuitry to isolate the latch
that caused the fail.

      This invention uses the system selftest and some compare and
count circuitry to take a selftest fail at cycle 102,400 and isolate
this failure to the first cycle in which the signature was wrong and
then to the latch that caused this first failing signature.

      With the functional card tester already in place, it followed
that one could put sockets on the high end memory card in order to do
failure analysis on the logic modules used on this card.  After this
was considered, it became obvious to etch a new card with sockets on
it that would support selftest on modules plugged into these sockets.
This card is called the Bug Isolation Tool (BIT) card.  It contains 4
sockets, a system clock generation module, the necessary connections
to run selftest, and the means to plug into the tester in the place
of the high end memory card.

      The scan-in lines going to two of the four sockets on the BIT
card are identical, producing parallel inputs.  With two modules
being selftested at the same time, it is given that the data coming
out of their scan-out lines should be identical at any given time.
On the boundary scan adapter card, circuitry was designed to compare
the scan-out lines of the two modules being tested to insure that
data being scanned out is the same.  At the same time the scan-out
lines are being...