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Digital-to-Analog Converter with Transition Time Control Resister

IP.com Disclosure Number: IPCOM000112726D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Nozawa, T: AUTHOR [+2]

Abstract

This article describes a digital-to-analog converter which is capable of changing its transition time by using an external resistor. The adjustment of the transition time is used for reduction of overshoot or ringing of the analog signal caused by inductance and/or impedance mismatch of a signal line.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 78% of the total text.

Digital-to-Analog Converter with Transition Time Control Resister

      This article describes a digital-to-analog converter which is
capable of changing its transition time by using an external
resistor.  The adjustment of the transition time is used for
reduction of overshoot or ringing of the analog signal caused by
inductance and/or impedance mismatch of a signal line.

      Fig. 1 shows an example of the circuit configuration.  The
digital-to-analog converter has a resistor connected to Vdd, which is
of selected value for a specific transition time.  A capacitor
connected parallel to the resistor is just for filtering a high
frequency noise.

      An example of the actual usage of an external resistor is
described by circuit schematics.  Suppose that the digital-to-analog
converter has a current-output architecture with
gate-voltage-controlled FET.  Here, a current source P-channel FET
flows a constant current and the current is routed by a current
steering switch.  Fig. 2 shows an exemplary circuit schematic of a
current steering switch which is driven by current-starved inverters.
In this Figure, (1) indicates the current source FET and the (2)'s
indicate current-steering switch FETs.  D-FF stands for delay
flip-flop, which feeds +data to the current-starved inverters.  In
order to limit the switching speed, FET gate nodes, GREFP and GREFN,
are to be controlled by a voltage generator, which is shown in Fig. 3
as an example.

      In the vol...