Browse Prior Art Database

Packet Logic for an Advanced Rendering Engine

IP.com Disclosure Number: IPCOM000112742D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 101K

Publishing Venue

IBM

Related People

Bowen, AD: AUTHOR [+3]

Abstract

A method for grouping pixel data from several sources into a common format for use by a memory controller is disclosed. The generation of "packets" allows the memory controller to operate at higher frequencies by eliminating complicated logic to handle many different data types.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Packet Logic for an Advanced Rendering Engine

      A method for grouping pixel data from several sources into a
common format for use by a memory controller is disclosed.  The
generation of "packets"  allows the memory controller to operate at
higher frequencies by eliminating complicated logic to handle many
different data types.

Background - In a rasterizer, the segment of the device responsible
for generating the pixels (the interpolators, for example) does not
often generate a stream of data that is optimized for the memory
controller.  In such systems, performance is lost as the memory
controller thrashes on the data stream.

      The optimization of the data stream is traditionally done in
the memory controller itself.  However, as the page mode cycle time
of VRAM and DRAM memory drops to 20 ns and 10 ns, the time available
to group the pixels into single memory access inline diminishes.  The
problem could be solved by pipelining the memory controller, but this
can lead to other inefficiencies, as well as providing a very
cumbersome and error-prone design.

The Solution - In order to alleviate this problem, a "packeting"
stage is introduced prior to the memory controller and modification
logic to group the generated pixels into packets of data that can be
handled efficiently by the memory controller.

      There are several means of sending data to a typical
rasterizer.  The data may be sent as points, vertices of lines,
vertices of triangles, or blocks of data called BLTs (BLock
Transfers).  The first stage of the rasterizer turns lines and
triangles into a stream of single points such that the first three
types of data (points, lines, and triangles) are decomposed into a
single data type.  BLT data is transferred to the rasterizer as a
stream of data corresponding to the values for each pixel in a
rectangular region.

      A simple memory controller accesses only a single pixel at a
time.  When this is the case, no additional optimization needs to be
done.  When the memory controller is designed to have access to a
plurality of pixels, then receiving pixels one at a time tends to
limit the utilization of the memory controller's bandwidth.  The
memory controller in the preferred embodiment can access up to 5
pixels simultaneously if the following rules are met:

o   The X-Div-5 value of each pixel must be the same
    (X-coordinate/5).

o   The Y-Div-16 value of each pixel must be the same
    (Y-coordinate/16).

o   Only one pixel per bank of memory may be simultaneously accessed.

      The first two requirements restrict the accessing of data to a
5*16 region of the screen.  In the preferred embodiment, this is done
to minimize the number of address lines.  Other designs may allow for
larger regions to be freely accessed.  The third requirement is based
on the degree of memory interlea...