Browse Prior Art Database

Automatic Cache Line Access Invalidating

IP.com Disclosure Number: IPCOM000112773D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Van Fleet, JW: AUTHOR

Abstract

Disclosed is a hardware mechanism to provide a correctness and performance enhancement to software cache coherency maintenance. Multiprocessing computer configurations which do not implement cache coherency in hardware are cheaper and scale easier than hardware cache coherence multiprocessors. This enhancement defines a mechanism for hardware to automatically invalidate cache lines; this provides assistance to software for higher performance and less chance for software error with less false sharing. Reference [1] describes the general technique of software synchronization with "lock and flush". References [2,3] are enhancements of that technique. This article is a further enhancement of the hardware mechanisms to implement that technique.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Automatic Cache Line Access Invalidating

      Disclosed is a hardware mechanism to provide a correctness and
performance enhancement to software cache coherency maintenance.
Multiprocessing computer configurations which do not implement cache
coherency in hardware are cheaper and scale easier than hardware
cache coherence multiprocessors.  This enhancement defines a
mechanism for hardware to automatically invalidate cache lines; this
provides assistance to software for higher performance and less
chance for software error with less false sharing.  Reference [1]
describes the general technique of software synchronization with
"lock and flush".  References [2,3] are enhancements of that
technique.  This article is a further enhancement of the hardware
mechanisms to implement that technique.

      In References (2,3), the hardware recognizes when specific
cache lines are introduced to the cache and maintains that
information on a cache line basis.  They include the definition of
mechanisms to flush/invalidate the appropriate cache lines.  This
article further enhances the mechanism by including a definition of
how the hardware can further assist by automatic invalidation of
cache lines:

o   it is appropriate to invalidate a cache line when the cache line
    does NOT have the bit set which indicates that it has been
    retrieved from main storage and is currently in the cache.

In other words, if the hardware would have set the indicator when the
cache...