Browse Prior Art Database

Circuit for Avoiding VCO Runaway in PLL

IP.com Disclosure Number: IPCOM000112778D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Nishikawa, H: AUTHOR

Abstract

Disclosed is a circuit for a phase-locked oscillator (PLL) to recover from deadlock. If the output of the Voltage-Controlled

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Circuit for Avoiding VCO Runaway in PLL

      Disclosed is a circuit for a phase-locked oscillator (PLL) to
recover from deadlock.  If the output of the Voltage-Controlled

Oscillator (VCO) divider is constant, this circuit forces the control
voltage of the VCO down so that its frequency goes down.

      If the frequency of the VCO goes higher than the maximum
operable frequency of the VCO divider for some reason, the output of
the VCO divider is stuck at either the low or high level, and the
phase detector makes the frequency higher.  Thus, the PLL loop will
never lock again.

      In the Figure, a counter A, two latches B and C, EXOR D, and
gates K and L are added to the usual loop circuit.  Counter A counts
the reference oscillator pulses, and sets latch B when a carry is
generated.  Latch C and EXOR D monitor the output of the VCO divider.
As long as the VCO divider is working, the output of EXOR D keeps
changing, thus the counter A and latch B are always reset.  But if
the output of the programmable divider is stuck, both the input and
output of latch C are the same, and the output of EXOR D stays high.
Thus, the counter A and latch B are not reset.  Then counter A starts
counting the reference clocks and sets the latch B.  Then the gates K
and L force the control boltage down so that the frequency goes down,
and the phase-locked loop works again.