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Read-Only Memory Self-Test Method

IP.com Disclosure Number: IPCOM000112792D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Ueda, M: AUTHOR [+2]

Abstract

This article describes a Read Only Memory (ROM) self-test method which uses an address counter and multiple data compressors. Each compressor performs data compression for interspersely populated memory cells such that a defect that causes multiple fails can be detected even with simple data compression algorithm that relies upon a "single stacked at fault" model.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Read-Only Memory Self-Test Method

      This article describes a Read Only Memory (ROM) self-test
method which uses an address counter and multiple data compressors.
Each compressor performs data compression for interspersely populated
memory cells such that a defect that causes multiple fails can be
detected even with simple data compression algorithm that relies upon
a "single stacked at fault" model.

      Failure mode which is unique to memory array structures, such
as wordline fail and bitline fail, typically causes a multibit fail.
This type of failure is difficult to detect using a conventional
self-test method, such as a signature analysis method that relies
upon a single stacked fault.

      This new self-test method provides a way to detect a
multiple-bit failure effectively, taking advantage of the spatial
locality of the defect which is characteristic of bitline failure and
wordline failure.  To accomplish this, multiple data compressors are
employed, as shown in Fig. 1.

      Every time the test clock is stimulated, word and column
address counters sweep the ROM address space and the data compressors
proceed with data compression of the read-out data.  Each data
compressor shown in Fig. 1 can take the form of an XOR and latch for
simplicity, as shown in Fig. 2.  After the entire address space is
accessed, the content of the latch in Fig. 2 is compared with
expected data that is generated from the user's 2 is compared with
expected data tha...