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Method to Allow the Sharing of I/O Port Addresses between a Floppy Disk Controller and an IDE Hardfile Controller within an IBM PS/2 Micro Channel System

IP.com Disclosure Number: IPCOM000112809D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 100K

Publishing Venue

IBM

Related People

Noll, MG: AUTHOR

Abstract

Disclosed is a method to allow the sharing of conflicting addresses between an Integrated Device Electronics (IDE) hardfile controller and a Floppy Disk Controller (FDC) within an IBM PS/2* Micro Channel* system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method to Allow the Sharing of I/O Port Addresses between a Floppy
Disk Controller and an IDE Hardfile Controller within an IBM PS/2
Micro Channel System

      Disclosed is a method to allow the sharing of conflicting
addresses between an Integrated Device Electronics (IDE) hardfile
controller and a Floppy Disk Controller (FDC) within an IBM PS/2*
Micro Channel* system.

      A FDC controls the reading and writing of data to/from a floppy
disk in the floppy drive.   From prior art, in order to set up the
FDC, eight I/O ports have  been  architected  with  addresses in the
range 3F0h - 3F7h.  Currently, all ports in this range except  the
one  at 3F6h are used by the FDC (Note the the port at 3F6h is listed
as reserved in the Intel 82077 spec).  Similar to the FDC, an IDE
controller controls the reading and writing of data from a hardfile
as well as the setting up of the hardfile.  An IDE controller has
architected I/O ports in the ranges 3F6h-3F7h and 1F0h-1F7h.  One can
readily see that both a FDC and an IDE controller,  when configured
in a Micro Channel system, would respond simultaneously  to  I/O
accesses to  address 3F7h.  If in the future the need arose to use
the reserved port of 3F6h in the FDC, there would also be an address
conflict at address 3F6h.  Note that this I/O address conflict is not
a concern in current ISA personal computer systems because the IDE
controller and the FDC share port 3F7h.  The IDE device only uses
bits 0-6 with bit 7 always in  the  high impedance state, and the FDC
uses only bit 7 with its bits 0-6 in the high FDC uses only bit 7
with its bits 0-6 in the high impedance state.  In Micro Channel
systems, the FDC utilizes more than bit 7 in port 3F7h, and hence,
sharing this port with an IDE device is not possible.   Note also
that in the future should the port at address 3F6h be used in the
FDC, there would also be a potential conflict in ISA systems.

      Shown in the Figure is a POS register which configures the
system IDE interface.  By programming bits 0-2 of this POS register,
one can specifically enable or disable  accesses to 3F6h and 3F7h.
This POS register is located at address 105 in group level B(denoted
by POS 105(94=BFh)).  The register  is  accessed by first wri...