Browse Prior Art Database

DRAM Flash Write Method

IP.com Disclosure Number: IPCOM000112831D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 84K

Publishing Venue

IBM

Related People

Katoh, Y: AUTHOR [+3]

Abstract

Disclosed is a flash write method for a Dynamic Random Access Memory (DRAM). A high level voltage Vcc, higher than internal high and level voltage Vdd + threshold voltage Vtp, is applied to dummy cells, bit lines are set to the Vdd high level. Namely all associated data cells along a word line, selected by a word decoder, are latched simultaneously as a flash write mode.

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This is the abbreviated version, containing approximately 52% of the total text.

DRAM Flash Write Method

      Disclosed is a flash write method for a Dynamic Random Access
Memory (DRAM).  A high level voltage Vcc, higher than internal high
and level voltage Vdd + threshold voltage Vtp, is applied to dummy
cells, bit lines are set to the Vdd high level.  Namely all
associated data cells along a word line, selected by a word decoder,
are latched simultaneously as a flash write mode.

      Fig. 1 shows memory cells and sense amplifier circuits of a
typical DRAM.  Fig. 2 presents a timing chart in the flash write
mode.  An equalized voltage line VEQ (9) supplies reference level
voltage for dummy cells (14,15).  VEQ line has a transistor (5) which
is connected to the external voltage source VRO (3).  This portion is
attached to do the signal margin test [*].  To do the flash write,
the external voltage source VRO (3) is set up to the high voltage
level (Vcc, over Vdd + Vtp), and a signal VRGN (4) is switched
on/off.  It does not conflict with a DRAM configuration in view of
its operations.

      In the access phase timing Ta, a signal VRGN (4) is turned on
and a transistor (4) is switched on to connect a reference level
voltage line VEQ (9) to the external voltage source VRO (3).
Transistors (13,17) are activated to supply reference level voltage
so that high voltage is applied on dummy cell nodes (12,16); i.e.,
the state "1" is stored in dummy cells (14,15).

      In the sensing phase timing Ts, a word line (1) and a countered
true reference word line (20) that has a dummy cell (15), selected by
the word decoder, become active.  The dummy cell (15) holds the high
level voltage Vcc and forces a bit line (19) to the high level.  Then
a complementary bit line (6) is becomes the low...