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Browse Prior Art Database

Multiple Means for Bus Access Apportionment

IP.com Disclosure Number: IPCOM000112833D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 230K

Publishing Venue

IBM

Related People

Brown, WW: AUTHOR [+2]

Abstract

Disclosed are several circuits embodying methods for allocating access to a computer system bus among various devices which may simultaneously request such access.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 26% of the total text.

Multiple Means for Bus Access Apportionment

      Disclosed are several circuits embodying methods for allocating
access to a computer system bus among various devices which may
simultaneously request such access.

      Fig. 1 shows a simplified version of a "feed forward" local
arbiter circuit, in which lower priority stages are disabled once
competition has been lost at a higher level.  This circuit is
associated with a particular device having an assigned arbitration
level.

      Fig. 2 shows a central arbiter circuit, which schedules
arbitration cycles within a specified time following a preempt
attempt by a device, or periodically whenever the PREEMPT signal is
continuously active.

      Fig. 3 shows a fairness circuit, in which a latch is provided
to interrupt a device request to its associated arbiter circuit
whenever a device is requesting arbitration while another device has
the channel tied up with a burst condition.  During an idle period,
all such latches are reset, and arbitration occurs in accordance with
the rules of the local and central arbiters.

      Fig. 4 shows etiquette logic which provides minimum bus access
time for a low priority device, such as the processor, before
preemption and arbitration can occur.

      Fig. 5 shows a gate which can be added to the logic of Fig. 4
to prevent preemption and arbitration when an interrupt signal is
present from a device which can be overrun.

      The operation of the local and central arbiter circuits will
now be discussed in an example assuming that the arbitration level
(ARB ID) of a device has been set to 6, and that operation is against
an arbiter elsewhere with an assigned arbitration level of 7.

      In Fig. 1, the arbitration level of the device is represented
by the signals appearing as inputs to inverters 8-0 through 8-3.  In
this example, these signals, ARB ID 3, 2, 1, and 0, are at levels 0,
1, 1, and 0, respectively.  The arbiter elsewhere transmits signals
along the arbitration bus 9, which is connected to the outputs of
NAND gates 10-0 through 10-3, each of which is an open collector
driver.  In this example, corresponding to an arbitration level of 7,
ARB3, ARB2, ARB1, and ARB0 at levels are 0, 1, 1, and 1 respectively.
An arbitration request from the device generates a DEVICE ARB REQ
signal, which sets preempt latch 12, thereby setting the -PREEMPT
signal active through inverter 13.

      In Fig. 2, in the central arbiter, the -PREEMPT signal is
applied as an input to an inverter 14.  When this signal becomes
active, the output of inverter 14 goes high, so that, if the BURST
signal is not also active, the output of AND gate 16 sets the data
input of arbitration latch 18 high.  The clock input to latch 18 is
provided by the ARBITRATION CLOCK signal, which is high for 300
nanoseconds and low for 7.5 microseconds.  With the next positive
edge of this signal, latch 18 is set with the high level its input,
so that t...