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Browse Prior Art Database

Power Control Relay for a Target System

IP.com Disclosure Number: IPCOM000112840D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Macy, RB: AUTHOR [+2]

Abstract

Disclosed is circuit using a solid state relay for turning the power to a target computing system off and back on, thereby performing a "cold boot" of the system. This circuit is operated by the Hardware Failure Simulator (HFS), which is used to apply simulated hardware failures, or "bugs" to the target system, testing the abilities of the diagnostic procedures of the target system to detect known simulated failures. The HFS must reboot the target system between simulated failures, assuring that simulated failures are thoroughly cleared to avoid affecting the operation of the target system with subsequent simulated failures. The HFS, with the Bug Analysis Research Tool (BART) interface between the host and target systems, can simulate a cold boot of the target system between each simulated failure.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Power Control Relay for a Target System

      Disclosed is circuit using a solid state relay for turning the
power to a target computing system off and back on, thereby
performing a "cold boot" of the system.  This circuit is operated by
the Hardware Failure Simulator (HFS), which is used to apply
simulated hardware failures, or "bugs" to the target system, testing
the abilities of the diagnostic procedures of the target system to
detect known simulated failures.  The HFS must reboot the target
system between simulated failures, assuring that simulated failures
are thoroughly cleared to avoid affecting the operation of the target
system with subsequent simulated failures.  The HFS, with the Bug
Analysis Research Tool (BART) interface between the host and target
systems, can simulate a cold boot of the target system between each
simulated failure.

      However, there are significant differences between a simulated
cold boot, which has the effect of a warm boot caused by pressing the
Ctl + Alt + Del keys of the target system, and an actual cold boot,
which is achieved by turning off and on the system power.  For
example, RAM memory cells are often not cleared by a warm boot, and
sometimes I/O ports contain left over data after a warm boot.  After
a warm boot, the Non-Maskable Interrupt bit contains the value it
last contained, instead of the value it contains after a cold boot.
With a cold boot, adapter cards on the system bus remain operational
until a channel reset occurs.  On some systems, two channel resets
are issued with a cold boot, while only one channel reset is issued
with a warm boot.  The duration of the channel reset can also be
shorter during the warm boot.  Control bits can differ between a warm
boot and a cold boot.  Some circuits and devices perform certain
self-testing...