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Browse Prior Art Database

Clock Generation and Control Circuitry

IP.com Disclosure Number: IPCOM000112857D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Bland, M: AUTHOR [+4]

Abstract

Described is a hardware circuit implementation that provides a means of generating and controlling high frequency clock phases at various clock rates from a single clock circuit. The clock circuit is implemented on a Very Large System Integration (VLSI) chip to achieve both functionality and testability at relative high clock rates.

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Clock Generation and Control Circuitry

      Described is a hardware circuit implementation that provides a
means of generating and controlling high frequency clock phases at
various clock rates from a single clock circuit.  The clock circuit
is implemented on a Very Large System Integration (VLSI) chip to
achieve both functionality and testability at relative high clock
rates.

      The Clock Generation and Control (CGC) circuitry utilizes a
Phase-Locked Loop (PLL) circuit in a clock module to synthesize the
required clock frequencies, thereby allowing high frequency sharp
pulses to be generated.  Phase splitter circuits are used to generate
lower frequency pulses.  For power management considerations, the CGC
circuit facilitates the control of the clock frequency, or stopping
the clock signal to the chip or a portion of the chip logic.

      The CGC circuit provides functions, such as:  a) generation of
all required clock frequencies; b) generation of required phases for
each clock frequency; c) control logic to support all clock stop
modes; d) generation of all required test clocks; e) control
circuitry to ensure testability and compatibility; and f) control
circuitry to support all test types.

      Fig. 1 shows a block diagram of the CGC circuitry.  It consists
of the following functional elements:  controllable PLL circuit 10;
divide by N circuits 11; phase splitters 12a, 12b and 12c;
synchronizers 13; various levels of clock gating logic 14a, 14b, 14c
and 14d; and speed governor circuit 15.

      Fig. 2 shows the circuit configuration of PLL circuit 10.  It
contains a control mechanism to either disable PLL circuit 10 (Fig.
1) or to stop the clock generation during system power off or under
global power management control.  Synchronizing latch circuits 13
within PLL 10 are used to synchronize the asynchronous control, or
power management signals to the system clocks, and to maintain the
integrity of the data stored in the latches during the clock stopping
and starting sequences.

      The CGC generates primarily all the required sets of clock
phases needed to operate a Central Processing Unit (CPU) and its
associated system support controllers from PLL circuit 10.  Two phase
splitters 12b and 12c are used to gen...