Browse Prior Art Database

Microcode/Sequencer Unit Verification Methodology

IP.com Disclosure Number: IPCOM000112859D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Glenn, S: AUTHOR [+3]

Abstract

Disclosed is a verification methodology used for the verification of the microcode/sequencer unit in RISC processors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Microcode/Sequencer Unit Verification Methodology

      Disclosed is a verification methodology used for the
verification of the microcode/sequencer unit in RISC processors.

      This unit verification methodology consists of two custom
C-Language programs and an existing Design Specification Language
(DSL) design design simulator.  The first program accepts a custom
formatted microcode testcase, simulates the testcase against an
internal representation of the processor's sequencer unit, and
generates a file containing the expected results for all sequencer
registers and signals as well as the original testcase contents.

      The second program processes this file and creates a timing
format testcase.  In short, this format consists of all input/output
signal definitions and input/output signal states for each Compiled
Enhanced Functional Simulator (CEFS) Simulation cycle.  For each
simulation cycle, the state of all input signals are set and the
state of all output signals are compared against the expects that
were produced by the first program.

      The above testcase is then simulated in CEFS using Simulation
Timing (SIMT).  SIMT simulates the testcase against the compiled
processor's sequencer unit DSL and microcode.

      The above methodology is repeated for each of the processor's
microcode trap points.  Fig. 1 depicts a typical RISC processor
interface to microcode.  Fig. 2 details the verification methodology
flow.