Browse Prior Art Database

Reiterative Parity Generator

IP.com Disclosure Number: IPCOM000112867D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Iachetta, R: AUTHOR [+3]

Abstract

Disclosed is a method for generating a parity bit for a Peripheral Component Interconnect (PCI) bus as data is read from an 8-bit device. The PCI bus requires the generation of one parity bit for 32 bits of data, together with the 4-byte enable bits, while previous bus structures used in personal computer require one parity bit per byte.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Reiterative Parity Generator

      Disclosed is a method for generating a parity bit for a
Peripheral Component Interconnect (PCI) bus as data is read from an
8-bit device.  The PCI bus requires the generation of one parity bit
for 32 bits of data, together with the 4-byte enable bits, while
previous bus structures used in personal computer require one parity
bit per byte.

      Fig. 1 is a schematic view of a computing system having system
ROM 10 connected to a PCI bus 12 through PAL* (Programmable Array
Logic) logic 14.  In a system like this, the logic required to
generate the parity bit for PCI bus 12 is too large to be implemented
easily in PAL logic 14.  However, since ROM 10 is read 8 bits at a
time, parity may be generated using a standard 9-bit parity generator
16.  As ROM 10 is read one byte at a time, the parity bit is
generated for that byte and returned as the 9th bit in a logic tree.
In this way, the parity bit is generated for the entire word by
reiterating the parity bit with every byte.

      Fig. 2 is a schematic view of a reiterative parity generator.
In general, the parity bit for a multi-byte access can be derived by
passing the individual bytes through a "byte plus one" bit generator
and returning the parity bit through the generator for the next byte.
In this example, data from an 8-bit data bus 18, extending from ROM
19, is sent to a 32-bit buffer 20 before the  data is sent out on a
32-bit bus 22.  As the 32-bit buffer 20 is being filled, the byte
indicators on line 23 are used to determine the byte lane into which
current data is to be placed.  Data from the 8-bit data bus 18 is
also directed to an 8-bit buffer 24.  The BYTE VALID signal qualifies
...