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Interface to a Floating Point Processor

IP.com Disclosure Number: IPCOM000112874D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 8 page(s) / 207K

Publishing Venue

IBM

Related People

Getzlaff, KJ: AUTHOR [+4]

Abstract

Described is a system in which the pipelines associated with a processor and a co-processor, such as a floating point processor, are coupled. Such a system allows the floating point processor to access the cache memory in only one cycle. In addition the system guarantees that a program is correctly interrupted when access exceptions or floating point exceptions occur during execution.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Interface to a Floating Point Processor

      Described is a system in which the pipelines associated with a
processor and a co-processor, such as a floating point processor, are
coupled.  Such a system allows the floating point processor to access
the cache memory in only one cycle.  In addition the system
guarantees that a program is correctly interrupted when access
exceptions or floating point exceptions occur during execution.

      Fig. 1 shows an overview of the system.  When the instruction
is loaded into the OP1 register 30 of the processor unit 10, it is
also passed to the floating point processor 20 via the OP1 Code bus
90.  The mode_1 signal 100 shows whether the instruction is a machine
instruction or whether a so-called forced operation mode is active.
Forced operations are those operations which stop the normal
execution of the machine instruction to carry out required tasks such
as the filling of the cache.  The mode_1 signal 100 is used to
indicate to the floating point processor 20 that the instruction
passed in the previous cycle of operation need not be processed.  The
execution of such an instruction will be therefore halted.

      A further signal, PU_Wait (not shown), will delay the
processing of the instruction if the processor unit 10 requires wait
cycles.  This arrangement ensures that the floating point processor
20 may begin processing an instruction without being delayed by a
cycle because of the processor unit 10.

      Fig. 2 shows an example of the passage of floating point (FLTP)
instructions through the pipeline stages of the processor unit 10 and
the floating point processor 20.  The pipelining for a floating point
instruction requiring operands from the cache is of the following
form:

1.  Generation of Operand Address (line 120)

2.  Cache Access (line 125)

3.  Bus transfer from cache to processor (line 135)

4.  Prenormalisation (line 145)

5.  Addition and Postnormalisation (line 155)

6.  Write the result to cache (line 160)

      The execution of conventional programs occurs serially.  By use
of the system described in the article, it can be ensured that the
setting of a condition code or the possible resumption of the program
occurs at the correct point.  This requires the application of a
FLPT_wait signal to the processor unit 10 when the floating point
unit 20 requires several cycles for the execution of an instruction.

      A wait cycle for the processor unit 10 is only required when
there are floating point operations to be performed which are
followed by a non floating point instruction, e.g. a branch
instruction requiring a correct condition code for the branch
decision.  The system is provided therefore with a further signal,
FLPT_busy, which is active whenever floating point instructions are
present in the pipeline.  This is illustrated in Fig. 3 which
illustrates a series of floating point instructions F1, F2, F3
followed by a branch instruction (BR...