Browse Prior Art Database

Solder Bump Formation on VIA Holes

IP.com Disclosure Number: IPCOM000112896D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Nakama, S: AUTHOR [+2]

Abstract

Disclosed is a method for building an eutectic solder bump on photo-via holes of Surface Laminor Circuit (SLC) carrier by utilizing the process for Printed Wiring Board build.

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Solder Bump Formation on VIA Holes

      Disclosed is a method for building an eutectic solder bump on
photo-via holes of Surface Laminor Circuit (SLC) carrier by utilizing
the process for Printed Wiring Board build.

      The Figure shows a process flow of the building method for
building bump.  After final via holes(2) are built on SLC
carrier(1),copper plating(3) is performed on insulator layer(4)
including via holes.  Plating resist film(5) is applied on it and
exposure/development treatment is performed to remove the resist on
via holes.  Solder bumps(6) are made in the via holes by electric
solder plating.  Then, the plating resist is removed and copper
etching process is performed.

      By utilizing the via holes as solder bump reserver,it is not
required to design the extra connecting pad for solder bump on the
surface and it is possible to get the stable amount of solder volume
for flip chip joining.

      The method of building solder bump on via holes is not limited
to the electric plating, and electroless solder plating or solder
paste is also applicable.