Browse Prior Art Database

Graphical Analysis of Integrated Circuit Placement Quality

IP.com Disclosure Number: IPCOM000112897D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Brennan, TC: AUTHOR

Abstract

A graphical technique to analyze integrated circuit placement quality is described.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Graphical Analysis of Integrated Circuit Placement Quality

      A graphical technique to analyze integrated circuit placement
quality is described.

      Integrated Circuits are frequently composed of circuits which
are automatically placed by a computer program.  One measure of the
quality of placement is what is known as cutline information.  This
cutline information helps evaluate whether the circuit is able to be
wired.  For example, a horizontal line is drawn every hundredth of
the chip height and the number of pins above and below are counted.
An example of an obvious problem is when the number of "cuts" at a
given point exceeds the number of wiring tracks available on the
chip, e.g., you have 1000 vertical tracks but your placement has 1400
pins above and below a horizontal cutline.  The problem with this is
that one has only textual information which is harder to interpret.

      The solution is to create a graphical display of the cutline
information directly on the current chip placement.  An example of
what would be overlayed a chip placement display is shown below:

***********************************************
*v                                            *
* v                                           *
*  v                                          *
*    vvv                                      *
*      v                                      *
*       vv                                    *   v = demand for
*         v                                   *       vertical wire
*          vv                           ...