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Programmable/Expandable Voter Circuit

IP.com Disclosure Number: IPCOM000112899D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 84K

Publishing Venue

IBM

Related People

Quintana, F: AUTHOR

Abstract

This disclosure describes a programmable voter circuit that is implemented using simple adder blocks in a unique way. The circuit encodes the number of active inputs into a binary value that is compared with a programmed binary value to determine when "n" number of inputs have become active. This circuit concept permits an easy way to design programmable voter circuits for any number of inputs by simply reapplying the concept.

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This is the abbreviated version, containing approximately 52% of the total text.

Programmable/Expandable Voter Circuit

      This disclosure describes a programmable voter circuit that is
implemented using simple adder blocks in a unique way.  The circuit
encodes the number of active inputs into a binary value that is
compared with a programmed binary value to determine when "n" number
of inputs have become active.  This circuit concept permits an easy
way to design programmable voter circuits for any number of inputs by
simply reapplying the concept.

      The circuit combines "adder" circuits in a unique way.  The
primary building block is a common 1 bit adder with Inputs: A, B, and
CARRY IN and Outputs: SUM and CARRY OUT as shown in Fig. 1.

      The concept is to apply the adder circuits in such a way that
the addition result never exceeds the number of inputs that can be
active.  For example, in a four input implementation, the four inputs
cannot be applied directly to a two bit adder because if they are all
active, the addition result is 6 when it should be 4.  This is
because a normal adder weights the bits differently.  Thus a two bit
adder would add 3 + 3 to arrive at 6.

      The implementation of the voter circuit is best described by
example.  The Encoder portion of the Voter is described below for a
circuit with four inputs (Fig. 2).  In the case of the 4 input
circuit, three of these adder blocks are used to implement the
circuit.  The first three primary inputs (In1, In2, and In3) are
applied to the A, B and CARRY IN inputs of ADDER 1.  The fourth input
(In4) is applied to the B input of ADDER 2.  The SUM output of ADDER
1 is applied to the A input of ADDER 2.  The CARRY IN of ADDER 2 is
held low (inactive).  Finally, the CARRY OUT of ADDER 2 is connected
to the A input of ADDER 3 and the CARRY...