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Empirical Model for Estimation of Theoretical Stuck Fault Testability

IP.com Disclosure Number: IPCOM000112902D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Milano, LC: AUTHOR [+2]

Abstract

Disclosed is an empirical model for use in the estimation of theoretical stuck fault testability of a particular portion of a logic design prior to its implementation. This information not only assists in the determination of the human resources needed to analyze untested portions of the design, but can also assist the logic design team by identifying, during the high level design phase, those components which are difficult to design without redundancy. The logic design team can then assign their most experienced designers to those components.

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Empirical Model for Estimation of Theoretical Stuck Fault Testability

      Disclosed is an empirical model for use in the estimation of
theoretical stuck fault testability of a particular portion of a
logic design prior to its implementation.  This information not only
assists in the determination of the human resources needed to analyze
untested portions of the design, but can also assist the logic design
team by identifying, during the high level design phase, those
components which are difficult to design without redundancy.  The
logic design team can then assign their most experienced designers to
those components.

      The model disclosed is based on the numerical characterization
of two aspects of the design environment:  the Design Potential for
Redundancy (DPR) and the Efficiency of Design Representation (EDR).

Following are the definitions of these terms and the presentation of
the model.

      Design Potential for Redundancy (DPR) - The design potential
for redundancy (DPR) takes into account several characteristics of
the future implementation of a digital component that must be
obtained from estimates by the high level designer.  These
characteristics are:  number of shift register latches, number of
primary inputs and outputs, the total number of 2-input AND-INVERT
equivalent circuits, and the number of AND-INVERT equivalent circuits
dedicated to data flow (as opposed to control flow).

The equation for the DPR is given as:

DPR = K * (latches + inputs + outputs) + data flow circuits

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