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Browse Prior Art Database

Implementing JTAG Test Instructions in Personal Computers

IP.com Disclosure Number: IPCOM000112915D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Hoch, G: AUTHOR

Abstract

Described is a hardware implementation to provide JTAG Test Access Port (TAP) instructions and boundary scan registers in an LSSD environment, as used in portable/laptop and similar personal computers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Implementing JTAG Test Instructions in Personal Computers

      Described is a hardware implementation to provide JTAG Test
Access Port (TAP) instructions and boundary scan registers in an LSSD
environment, as used in portable/laptop and similar personal
computers.

      The concept primarily involves single chip integration of high
performance types of microprocessors along with functions involving
Direct Memory Access (DMA), memory control and other peripheral
Input/Output (I/O) functions.  It is designed to incorporate JTAG TAP
instruction and boundary scan registers in an LSSD environment when
either; a ) no L1/L2* latches exist in the circuit library, or b)
usage of L1/L2* latches is not possible due to circuit area
constraints.

      Generally, registers in an LSSD design methodology utilize an
L1/L2* latch pair to implement each bit in these registers.  Usage of
L1/L2* latch implies the need for this type of latch in the cell
library, as well as additional circuit areas since the latch is
large.  The concept described herein eliminates the use of the L1/L2*
latches and replaces them with standard L1/L2 latches.

      Documentation for implementing JTAG instruction and boundary
scan registers in an LSSD environment exists as part of the ASIC
library and the IEEE Standard 1149.1 Specification.  Both
implementations use a method whereby an L1/L2 latch feeds a L1/L2*
latch to create each bit of the desired register.  Fig. 1 shows a
block diagram o...