Browse Prior Art Database

Content Addressable Memory

IP.com Disclosure Number: IPCOM000112916D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Aipperspach, TG: AUTHOR [+2]

Abstract

A means to provide a high performance solution for a Content Addressable Memory in a BiCMOS technology is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Content Addressable Memory

      A means to provide a high performance solution for a Content
Addressable Memory in a BiCMOS technology is disclosed.

      Fig. 1 shows the Content Addressable Memory (CAM) block
diagram.  The cam consists of a write decoder (shared), the valid
cells, the key cells, a set of latches, a priority decoder, an
address generation block, and the data cells.  When the read key is
applied, the key is compared with the content of the all key cells
simultaneously.

      Fig. 2 shows the key cell.  Devices P5, P10, P11, P12, N84,
N94, N96, N97, and TUP0 make up the dotted bipolar emitter compare
circuitry.  All the key cells and the valid bit in a particular key
are dotted at node 10.  By dotting the emitters in this fashion, very
high performance on wide compare keys is realizable.

      Referring back to Fig. 1, the dotted compare lines are latched
up and feed the priority decoder.  The priority decoder insures only
one valid match is propagated to the address generation circuits and
the data cells.  It also produces a signal that signifies if a hit
has occurred or not.  The address generation circuits produce the
address at which the match occurs.