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Scheme for Low Loss Hot Plugging and Fault Protection in Switch Mode Power

IP.com Disclosure Number: IPCOM000112923D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 108K

Publishing Venue

IBM

Related People

Keidl, SD: AUTHOR

Abstract

Disclosed is a scheme for hot plugging and fault protection in power converters.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Scheme for Low Loss Hot Plugging and Fault Protection in Switch Mode
Power

      Disclosed is a scheme for hot plugging and fault protection in
power converters.

      This scheme provides, with a minimum amount of circuitry, the
following requirements of hot plugging and fault protection in DC to
DC power converters:

o   A series switch function to isolate pulse-width modulation (PWM)
    converter circuitry from input power

o   Delayed application of power to a PWM converter after converter
    card hot plugging

o   Instantaneous power removal from a PWM converter if a fault
    condition is sensed

o   Controlled inrush current from the input power bus to the
    converter.

      An N channel power FET is used as the hot plug switch element.
To provide the gate voltage to turn this N channel FET on hard enough
to provide a sufficiently low "on" resistance, a capacitive charge
pump is used.  The existing PWM circuitry in a typical DC to DC
converter is used to provide the drive for the charge pump.  This
circuit works even though the PWM circuitry is not running when the
series FET is first turned on to start the PWM engine.  The charge
pump circuitry is also used to provide the turn on delay for
converter hot plug requirements, and to regulate the rate of rise of
converter input current.  Finally, the series switch can be turned
off very fast to kill power to the PWM engine under fault conditions,
a requirement for robust design.  No single component failure can
connect the regulator input voltage bus to the output.

The basic circuitry is shown in Fig. 1.  The PWM converter circuitry
is abbreviated for clarity.  When the card containing this circuitry
is first plugged into the system, series switch Q1 is off.  Capacitor
C5 begins charging through resistors R3 and R4.  When the gate
threshold voltage of Q1 is reached (about 3 volts), Q1 begins to turn
on.  The (R3+R4)*C5 time constant, therefore, establishes the hot
plug turn on delay of the converter.  Q1 conduction causes the source
terminal voltage of Q1 (Pt.  A) to rise.  When this voltage has
reached the under voltage lock out threshold of the enabled PWM
engine, transistor Q3 begins to switch.  This switching starts charge
pump action via C2,C5...