Browse Prior Art Database

Scheme to Interface Various Vendor External Microwire Compatible EEPROMs to a C2 Security Controller

IP.com Disclosure Number: IPCOM000112934D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Clarke Jr, GL: AUTHOR [+4]

Abstract

Disclosed is a method to give C2 security controllers the flexibility to interface with more than a dozen different versions of EEPROMS currently available from various manufacturers. This invention, when incorporated within a C2 security controller design, would give computer manufacturers the ability to use one version of a C2 security controller design across their product lines, while at the same time giving them flexibility to interface different size

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Scheme to Interface Various Vendor External Microwire Compatible
EEPROMs to a C2 Security Controller

      Disclosed is a method to give C2 security controllers the
flexibility to interface with more than a dozen different versions of
EEPROMS currently available from various manufacturers.  This
invention, when incorporated within a C2 security controller design,
would give computer manufacturers the ability to use one version of a
C2 security controller design  across their product lines, while at
the same time giving them flexibility to interface different size

EEPROMs depending on the cost or performance needs of any one
particular product.

      The U.S.  government has legislated that after January 1, 1992
all personal computers used for storing data for government purposes
must have a minimum security level of C-2.  Typically, a C2 Security
controller provides a four pin serial interface to "talk to" an
external Microwire(TM National Semiconductor) compatible EEPROM.  The
system security password, other reserved passwords, the IPL sequence,
and Vital Product Data are stored in the EEPROM.   The four pins
which make up this interface are EEPROM_CS, SERIAL_DATA_IN,
SERIAL_DATA_OUT, and SERIAL_CLK.  The EEPROM provides random access
to its data, so every transfer contains two bytes which include
address and command information, and two bytes of input/output data.
The address and data transfers are paced by the SERIAL_CLK.  Fig. 1
shows a partial listing of EEPROMs that could be potentially
supported by...