Browse Prior Art Database

Automated Simulation Method for VLSI Designs

IP.com Disclosure Number: IPCOM000112938D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Kalman, DA: AUTHOR

Abstract

Described is an automated simulation method that provides the ability to run a random set of test cases and to automate the execution and test result analysis of Very Large Semiconductor Integrated (VLSI) designs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Automated Simulation Method for VLSI Designs

      Described is an automated simulation method that provides the
ability to run a random set of test cases and to automate the
execution and test result analysis of Very Large Semiconductor
Integrated (VLSI) designs.

      Typically, complex VLSI designs require an extensive amount of
hardware simulation to verify the timing and functionality of the
designs.  Managing the test case variation and simulation results can
become a monumental task that can be handled by means of an automated
process.  The concept described herein implements an automated
process designed to reduce development time and to analyze simulated
results.  In addition, the concept provides a means of providing
regression test cases that can be run successfully before the designs
are ever produced in silicon.

      Part of the simulation case development can be eliminated by
using control variables in the simulation case set by an automated
case driver.  For example, a generic test case can be written to test
the VLSI chip I/O ports.  The test case would be written as follows:

       /* Test Case Name: GENIOTEST - Generic I/O Port test */
             Do For all I/O Ports
               Port# = First Port#
               Write I/O Port
               Read I/O Port
               If Write Data not equal to Read Data
               then do
                 Display I/O Port (Port#) Defective
                 Set Error Status
               end
               CALL SAVESTAT(TESTNAME)
        /* Save Simulation Test Case Results */

      Now a test case driver can be used to do variations of the
GENIOTST by modifying parameters in the model that actually performs
the I/O operations.  The model has to be written with the flexibility
to control various timing parameters.  A test case driver would be
written as follows:

       /* Test Case Name: DRIVER - Runs all test cases in
    regression bucket */
            Pass = 1
            Do For all passes
               If Pass = 1
              then do
                 Set Slot size as 16 bits in Micro Channel* (MC)
                 Set Timing parameters as Nominal in MC Model
                 Disable MC Streaming data in MC Model
                 Set clock to VLSI chip to 50.50 duty cycle
                 ect.
               end
               If Pass = 2
               then do
                 Set Slot size as 32 bits in MC Model
                 Enable MC Streaming data in MC Model
                 Set clock to VLSI chip to 40/60 duty cycle
                 ect.
   ...