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Fault Injection during Code Test by a Memory Interposer Technique

IP.com Disclosure Number: IPCOM000112946D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Clayton, JE: AUTHOR [+8]

Abstract

Disclosed is a technique facilitating the testing of Power-On Self-Test (POST) and memory diagnostics by injecting memory faults into the system under test. This is done to ensure that such faults are detected and to verify that appropriate actions are taken when such failures are encountered. With this technique, a printed circuit board, called a "memory interposer," devised for fault injection, is plugged directly into one of the Single In-Line Memory Module (SIMM) sockets of the system within which code is being tested. If desired, additional circuit boards of this type may be plugged into additional SIMM sockets.

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This is the abbreviated version, containing approximately 52% of the total text.

Fault Injection during Code Test by a Memory Interposer Technique

      Disclosed is a technique facilitating the testing of Power-On
Self-Test (POST) and memory diagnostics by injecting memory faults
into the system under test.  This is done to ensure that such faults
are detected and to verify that appropriate actions are taken when
such failures are encountered.  With this technique, a printed
circuit board, called a "memory interposer," devised for fault
injection, is plugged directly into one of the Single In-Line Memory
Module (SIMM) sockets of the system within which code is being
tested.  If desired, additional circuit boards of this type may be
plugged into additional SIMM sockets.

      The SIMM target for fault injection plugs directly into the
memory interposer.  When the no fault is to be produced, all signals
at the SIMM socket are routed to a SIMM memory module without
modification.  Control of various aspects of the testing is achieved
using an attached host system.

      Address inputs to the memory module are monitored.  When a
memory cycle occurs with an address matching the address of a target
fault, the fault becomes active.  For the cycle in which a fault is
active, a designated data line is forced to a predetermined fault
level, being forced high, low, or inverted.  The fault remains active
only during the memory cycle in which the fault address was detected.
The granularity achievable with this technique is determined by the
granularity of the address lines that are monitored.

      According to a first method of monitoring the address lines,
only the Channel Address Strobe (CAS) address is monitored.  A 12-bit
code from the host system is stored in a latch resident on the memory
interposer card.  A hardware comparator is used to compare the
latched fault address with the CAS address incident at the SIMM
socket during a SIMM memory access cycle.  The SIMM ID lines can be
modified under control of the host system to reconfigure a SIMM
memory module to a size of 1, 2, or 8 me...