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Browse Prior Art Database

Dual-Interface Wrap Test

IP.com Disclosure Number: IPCOM000112959D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 169K

Publishing Venue

IBM

Related People

Bergey, AL: AUTHOR [+3]

Abstract

Disclosed is a wrap test for master-slave half-duplex interface with differential drivers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

Dual-Interface Wrap Test

      Disclosed is a wrap test for master-slave half-duplex interface
with differential drivers.

This invention is a test mechanism for the interface shown in Fig. 1.

The interface contains the following signals, as shown in Fig. 1.

1.  Two byte-wide data transfer busses

2.  Outbound control signals to provide control information from the
    master to the slave.

3.  Inbound control signals to provide control information from the
    slave to the master.

All of these signals use differential drivers and receivers.

The interface works in one of two operating modes:

1.  For command and status transfer, one of the two byte-wide data
    transfer busses (bus 0) is configured for transfer from the
    master to the slave, while the other (bus 1) is configured for
    transfer from the slave to the master.  These busses, together
    with the Controls In/Out are controlled by microcode.  This
    allows full-duplex, relatively slow transfer of information
    between the master and the attached slave.

2.  For data transfer, both data transfer busses are configured to go
    in the same direction (from master to slave for WRITE, from slave
    to master for READ).  These busses, together with the control
    lines, are controlled by data transfer hardware.  This allows
    half-duplex, high-speed transfer of information between the
    master and the attached slave (Fig. 2).

      The command and status transfer mode has been tested with wrap
techniques for many years.  Wrap-testing a full-duplex, microcode
controlled interface is not difficult.  Bus 0 wraps to Bus 1, and the
Control Out signals wrap to the Control In signals.  This is shown in
Fig. 2.

      However, testing this interface only in its full-duplex
configuration is not sufficient to ensure a high quality product.
The full-duplex configuration does not test all parts of the hardware
and does not test them at high speed.  A test of the interface in the
half-duplex data transfer mode is required to fully exercise the
logic.

      In the past, data transfer mode testing has been done either
with a real slave, or with a simulator.  The master under test is
cables to the slave or slave simulator, and data is transferred to or
from it using the data transfer protocol.  This technique has certain
disadvantages, however:

1.  A slave or slave simulator costs money.  Letting the master test
    itself costs only the expense of a wrap cable.  This represents a
    significant manufacturing cost savings.

      In spite of these advantages, no one has successfully tested
the interface data transfer mechanism using a wrap technique.  This
is due to the following difficulties:

1.  The interface data transfer mechanism is a half-duplex mechanism.
    It transfers data from the master, or to the master, but never
    both at the same time.

          Wrap tests must have both...