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Implementation Independent DRAM Addressing Technique

IP.com Disclosure Number: IPCOM000112971D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Elliott, JC: AUTHOR

Abstract

A DRAM addressing method which is independent of the Row/Column organization of the part is described.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Implementation Independent DRAM Addressing Technique

      A DRAM addressing method which is independent of the Row/Column
organization of the part is described.

      By manipulating the Row/Column address bits multiplexed on the
bus one can address a memory module based only on the module's
address space and not on the component's Row and Column address
implementation.  The following example deals with a 4M address space
but if applicable to any size address space.

      In order to address a 4M region, 22 address bits are needed.
There are two basic addressing arrangements for this 4M region; one
requires 11 row and 11 column address bits, and the other is 12 row
and 10 column bits.  By multiplexing the Row and Column address sent
out as shown below, either memory type can be used.

      If an 11 row, 11 column part is used, the memory module ignores
the MSB, or Most Significant Bit, of both the Row and Column
addresses.  This leaves the 22 unique bits needed to address the
region.  For a 12 Row by 10 part, the memory module uses all 12 bits
of the Row address and ignores the top 2 MSB's of the Column address.
This again leaves the 22 unique bits needed to address the region.
In fact, the two module organization types can be addressed and used
in the same system.