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Micro Channel Enhancements for Personal Computers

IP.com Disclosure Number: IPCOM000112975D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 128K

Publishing Venue

IBM

Related People

Farrell, JK: AUTHOR [+7]

Abstract

Described is an architectural implementation to provide enhancements to the Micro Channel* (MC), as used in Personal Computers (PCs). The first enhancement enables a host to access memory mapped MC adapters in address constrained environments. The second enhancement provides the MC with a deep/shallow bus interface module.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Micro Channel Enhancements for Personal Computers

      Described is an architectural implementation to provide
enhancements to the Micro Channel* (MC), as used in Personal
Computers (PCs).  The first enhancement enables a host to access
memory mapped MC adapters in address constrained environments.  The
second enhancement provides the MC with a deep/shallow bus interface
module.

Enhancement #1 - Host Access to Memory Mapped MC Adapters in
                   Address Constrained Environments.

      In prior art, MC adapters with multiple megabytes of local
memory were mapped to MC address space and could not be accessed by
the host processor in an address constrained environment, such as in
16-bit OS/2* applications, or when the adapter was in a 16-bit slot.
Also, 16-bit environments have only 24-bits of address which limited
the total MC addressability to 16 megabytes.

      The concept described herein provides a means that allows full
access to all of the adapters local address space in an address
constrained environment.  The concept is implemented in two 32-bit
registers located in the MC I/O space.  The two registers are called
Host Slave Base address Register (HSBR) and memory data register
(MDATA).  The HSBR serve as a pointer to a local bus address location
and the MDATA operates as a data port by which the location pointed
to by the address within the HSBR can be written or read.  Any MC
master can load a local bus address into the HSBR, then subsequently
access the MDATA register to read and write memory of devices that
reside on the local bus of the adapters.  Each access to the MDATA
register will automatically increment the contents in the HSBR by the
number of accesses.  The data port mechanism has the following
advantages for a MC adapter:

o   Allows adapter address space to be fully accessed in address
    constrained environments, such as 16-bit OS/2.

o   Mapping of a shared storage window in the MC memory address space
    is not required for MC masters (primarily intended for the host
    processor) to access the entire local bus address space of an
    adapter.  Therefore, the MC memory address space is not required.

o   The auto-incrementing feature of the HSBR allows the system host
    to download blocks of code to the adapter by simply initializing
    the HSBR once, followed by repeated writes to the MDATA register.

o   Since the local bus address is written directly into the HSBR and
    the MDATA register is at a fixed MC address, no address
    translation is required from the MC memory address to the local
    bus address.

o   The direct access into local bus address space without address
    translation creates a simple, straight forward mechanism to debug
    a subsystem adapter.

Enhancement #2 - MC Deep/Shallow Bus Interface Module

      Typically, bus master adapter circuit cards for MC systems can
be classified as deep a...