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Superscalar Interrupt Garbage Collection Scheme

IP.com Disclosure Number: IPCOM000112977D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 124K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+3]

Abstract

An orderly return from an interrupt is very crucial in microprocessor design. Restoring the state of the processor to what it was before the interrupt is referred to as Garbage Collection. The multi-processor implementation adds to the Garbage Collection complexity. This invention disclosure offers a unique alternative that eliminates much of the complexity associated with other methods.

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Superscalar Interrupt Garbage Collection Scheme

      An orderly return from an interrupt is very crucial in
microprocessor design.  Restoring the state of the processor to what
it was before the interrupt is referred to as Garbage Collection.
The multi-processor implementation adds to the Garbage Collection
complexity.  This invention disclosure offers a unique alternative
that eliminates much of the complexity associated with other methods.

      Interrupts are commonly used on microprocessors to allow
interruption of the program in execution.  Normally,  after the
interrupt is serviced,  it is intended that the program execution
proceed as if no such interruption had occured.  It is crucial that
the microprocessor register contents be restored to their
pre-interrupt state.  Here, this restoring of the register contents
is referred to as Garbage Collection.  In the multi-processor
environment,  there are many instruction in execution at any given
time,  thus adding to the complexity of the Garbage Collection.

      A typical RISC processor opcode format is:  OPC   RT,RA,RB.
Where,  OPC is the opcode,  RT, RA and RB are the target and source
registers respectively.  This architecture example makes use of 32
Floating point, and 32 fixed point registers.  However,  the number
of physical registers implemented is 64 for each.  The source and
target registers of the instruction stream get renamed to physical
registers and get dispatched to execution units as control words.
The Superscalar Control Unit (SSC) will look at some pointer tables
and replace the architected source or target register of the
instruction with a physical register location that it reads from the
tables.  So if RA of an instruction is FPR 23,  it might be FPR-PH 54
when it gets to execution stage.  Any subsequent references to this
register should use 54 until it is renamed again.  Please refer to
Fig. 1.

      As can be seen from the above picture,  the SSC will receive
the instruction stream and will use the CVT,  AXXR,  and RXXR to
construct the control words.  Once the control words are generated
they are sent to IQ,  and get dispatched from there to Execution
Units (EU).  At this point the order totally depends on the
instruction mix and how busy the EUs are,  and the execution order
might not match the incoming instruction stream order (Fig. 2).

      The control word generated by the SSC has source and target
register fields such as the instructions themselves.  However,  these
are physical registers rather than architected (referred to as
logical here).  For every instruction, the SSC will read the contents
of RXXR, pointed to by the source registers of the instruction and
put them in the source register address field of the control word.
Any subsequent instructions that reference architected register 0
must use the contents of RXXR location 0 upon control word
generation.  The SSC will also rename the target...