Browse Prior Art Database

Localized Decoupling Circuitry

IP.com Disclosure Number: IPCOM000112992D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Cronin, DR: AUTHOR [+2]

Abstract

Described is a hardware implementation to provide localized decoupling in Very Large Scale Integrated (VLSI) circuits. The implementation maximizes circuit space within VLSI chips to decouple power supplies, increase wafer planarity at the gate level to aid manufacturing of the chips, and provides for repeatable poly density for manufacturing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Localized Decoupling Circuitry

      Described is a hardware implementation to provide localized
decoupling in Very Large Scale Integrated (VLSI) circuits.  The
implementation maximizes circuit space within VLSI chips to decouple
power supplies, increase wafer planarity at the gate level to aid
manufacturing of the chips, and provides for repeatable poly density
for manufacturing.

      In prior art, as the magnitude of power supply voltages were
reduced in VLSI circuitry, it has become critical to guarantee noise
free supply rails.  This has been achieved by using various methods
for creating decoupling capacitors, such as utilizing a large N-well
for a capacitor, or through the use of a large poly ring over thin
oxide, plus a diffusion substrate contact ring that encircled the
chip.  The major difficulty with these methods was that the
implementation resulted in additional circuit chip area.  Basically,
additional die size was traded for additional decoupling capacitance.

      The concept described herein utilizes the available internal
area of all VLSI chips by increasing the decoupling capacitance with
no impact to the die size.  The implementation involves one more
layout modification to the design to take place prior to
manufacturing or mask generation.  It would not be started until a
clean design rule check (DRC) has been accomplished.  The
implementation involves creating poly thin oxide capacitors hooked to
the power supply in all unused thic...