Browse Prior Art Database

Signal Timing for a Floppy Disk Drive Controller

IP.com Disclosure Number: IPCOM000112997D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 119K

Publishing Venue

IBM

Related People

Hardbarger, DL: AUTHOR [+3]

Abstract

Disclosed is a method providing timing of the VCO_SYNC signal in a floppy disk controller to reduce the probability of a data recovery error caused by a phase-locked loop mislock condition. Write splice gaps are bypassed in a single sector read operation as well as in a full track read operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Signal Timing for a Floppy Disk Drive Controller

      Disclosed is a method providing timing of the VCO_SYNC signal
in a floppy disk controller to reduce the probability of a data
recovery error caused by a phase-locked loop mislock condition.
Write splice gaps are bypassed in a single sector read operation as
well as in a full track read operation.

      In rotating DASD devices (Direct Access Storage Devices), the
smallest addressable unit of data on the medium is known as a block,
or sector.  Sectors are arranged circumferentially around the
recording medium, with a group of sectors at a particular radius
being known as a track.  Tracks are in turn arranged concentrically
on each side of the medium.

      Fig. 1 is a diagrammatic view of the track format of a 2.88MB
floppy disk.  Each sector is divided into an ID field and a data
field, with each of these fields being preceded by a Gap field and a
Phase-Locked-Loop (PLL) Synchronization (Sync) field.  The Gap fields
provide an area in which the read/write heads of the drive can be
turned on and off without corrupting the ID, Data, and Sync fields,
so that an overwrite can occur on a sector basis instead of only on
the basis of a full track.  Although the Gap fields are cleanly
written during the original track formatting process, Gap 2 becomes
corrupted with "write splices" as the write and erase heads are
turned on to update the adjacently following data field, and Gap 3
becomes similarly corrupted when the write and erase heads are turned
off after updating the adjacently preceding data field.

      The purpose of the PLL Sync field is to provide a constant
high-frequency data pattern allowing the diskette controller PLL to
quickly adjust its phase and frequency to match the incoming data
stream.  When the PLL is locked to the data stream, the information
in the ID and Data fields can be decoded.  A PLL is required because
the readback frequency varies with the effects of variations in motor
speed, so that a constant-frequency reference cannot be used for data
separation.

      Unfortunately, the PLL can become unlocked when subjected to
write splices and other discontinuities occurring in the gaps.  Once
unlocked, the PLL attempts to relock to the incoming data stream.
However, this effort may fail because the PLL has been pulled so far
off the correct frequency that it cannot relock within the next PLL
Sync field, or because the PLL locks to a harmonic of the data
frequency, never relocking until the data stream is replaced by the
center-frequency reference.  When either of these conditions occurs,
data cannot be recovered from the medium, and errors are reported to
the system operator.

      To minimize this problem, conventional diskette controller
chips provide a means for masking the bit stream from the PLL when
the read head is over the Gap f...