Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Asynchronous Set-on-Event and Clear-on-Read Flag

IP.com Disclosure Number: IPCOM000113000D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

Knepper, L: AUTHOR

Abstract

Disclosed is a double-latched asynchronous set-on-event and clear-on-read latch function using scannable LSSD polarity-hold latches. A forced asynchronous set/reset capability built into the latch is not required. A circuit requiring this latch function, such as a real time clock, may be implemented in a standard cell technology with basic LSSD polarity-hold latches, forming a scannable, and therefore more testable, design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Asynchronous Set-on-Event and Clear-on-Read Flag

      Disclosed is a double-latched asynchronous set-on-event and
clear-on-read latch function using scannable LSSD polarity-hold
latches.  A forced asynchronous set/reset capability built into the
latch is not required.  A circuit requiring this latch function, such
as a real time clock, may be implemented in a standard cell
technology with basic LSSD polarity-hold latches, forming a
scannable, and therefore more testable, design.

      A conventional battery backed-up real time clock operates for
at least five years, running off a battery having a capacity of 850
mA-hr or less.  While the power restrictions of a portable personal
computer require that virtually no circuits in the real time clock
may run off the 33 MHz system clock, the 32.768 KHz free-running base
oscillator of the real time clock is too slow for use as a LSSD clock
with circuitry interfacing with other circuits operating at the
frequency of the system clock.

      In a conventional real time clock, the interrupt FLAG register,
Register C, provides flags which are set on events synchronous to the
32.768 kHz base clock but asynchronous to the 33 MHz system clock.
These flags are read by system logic, with the act of reading the
FLAG register clearing this clear-on-read register.  To ensure that a
flag is not lost because it occurs as the FLAG register is read, the
flags are double-latched, so that a first stage may be set by an
event, while the values of the register during a read strobe are held
in a stable state.  A second stage is asynchronously blocked from
being set if an event occurs while the read pulse is active.  It this
occurs, the second stage is set as soon as the read strobe is taken
away, since the FLAG register can be read again before another cycle
of the base clock.  For these reasons, conventional real time clocks
use asynchronous, non-LSSD edge-triggered latch techniques, allowing
latches to be set and cleared asynchronously to either the fast
system clocks or the slow time base clocks.  However, the testability
of such a circuit is very low unless an exhaustive set of test
vectors is used, verifying each function and each stuck fault that
can impact the function seen at the pins.

      The Figure is a logic schematic diagram of a scannable
asynchronous-set, clear-on-read latch, including three stages of L1
and L2 latches.  The LSSD clocks, ACLK, BCLK, and CCLK are driven by
the chip test logic (not shown).  The clock enable input EN is used
as the latch functional clock.  Only the L1 latches are functionally
checked, with the L2 latches being used in a transparent mode.  This
method allows the synthesis tools to operate, since the synthesis
tool does not allow clock gating outside the latch.  However, a
non-gated clock latch type can be used with an external AND gate to
achieve the same results.

      In the test mode, the test patterns cause the clock enable
input EN o...