Browse Prior Art Database

Microcomm Networking Protocol Class Transition Mechanism

IP.com Disclosure Number: IPCOM000113003D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 117K

Publishing Venue

IBM

Related People

Mandalia, BD: AUTHOR [+3]

Abstract

Disclosed is a class transition mechanism for a communication adapter using a multi-processing environment, having a Microcomm Networking Protocol (MNP) [*] framing function separated onto a separate processor, referred to as the Protocol Processor. The Host Processor controls MNP functions other than framing. This mechanism is required to effect a Class 2 to Class 3 switch requested by the Host Processor, without a loss of data resulting from incorrect framing types. This mechanism ensures that either Class 2 or Class 3 data will be received by the separate Protocol Processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Microcomm Networking Protocol Class Transition Mechanism

      Disclosed is a class transition mechanism for a communication
adapter using a multi-processing environment, having a Microcomm
Networking Protocol (MNP) [*]  framing function separated onto a
separate processor, referred to as the Protocol Processor.  The Host
Processor controls MNP functions other than framing.  This mechanism
is required to effect a Class 2 to Class 3 switch requested by the
Host Processor, without a loss of data resulting from incorrect
framing types.  This mechanism ensures that either Class 2 or Class 3
data will be received by the separate Protocol Processor.

      The Figure shows schematically a Protocol Processor 10
connected to a Host Processor 11, which includes the MNP application
12.  Interfacing between these Processors is performed as the Host
Processor issues control blocks to the Protocol Processor device
driver 13.  A Configuration Services Control Block (CSCB) is issued
to setup or configure a particular data channel for the Protocol
Processor.  A Transmit Control Block (TCB) is called by the Host
Processor to effect the transmission of a data frame or Protocol Data
Unit (PDU).  A Receive Control Block (RCB) is issued to allocate
memory for the reception of a PDU.

      The Universal Synchronous Receiver-Transmitter (USRT) function
14 and the Universal Asynchronous Receiver-Transmitter (UART)
function 16 are implemented in microcode running on Protocol
Processor 10.  The USRT function 14 provides for both receiving and
transmitting synchronous serial communications, while the UART
function 16 provides for both receiving and transmitting asynchronous
serial communications.  Protocol assist hardware may optionally be
used, and the architecture may be used to process many MNP channels
concurrently.  The modem function 17 is also provided within Protocol
Processor 10.

      Before a frame or PDU is transmitted, a Service Routine of the
MNP Transmit Finite State Machine (FSM) 18 of Protocol Processor 10
is called by Operating Kernel 20.  This routine checks the
Configuration Services Control Block (CSCB) command from the Host
Processor 11 to determine whether MNP Class 2 or 3 is specified.
While Class 2 is normally initiated, Class 3 may be initiated for
diagnostic use.

      Before a PDU is received, the MNP Receive FSM 22 is called by
Operating Kernel 20.  Receive FSM 22 typically receives Class 2 data
from a programmable UART function 16 through a circular queue
(URECQUE).  Additionally, the UART function 16 passes raw binary data
to be processed as synchronous Class 3 data into another circular
queue (UREC3QUE).

      The Class Monitor Routine 24 (CLASSMON) runs as another
Protocol Processor task, during which Protocol Processor 10 receives
raw data from the circular queue UREC3QUE,...