Browse Prior Art Database

Method for Interrupt Sharing with IDE Hard Files in IBM PS/2 Systems

IP.com Disclosure Number: IPCOM000113010D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Andric, A: AUTHOR [+5]

Abstract

Disclosed is a method that allows the interrupt request of an IDE hardfile to be shared with another device (e.g., SCSI hardfile) on interrupt level 14 within an IBM PS/2* system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Method for Interrupt Sharing with IDE Hard Files in IBM PS/2 Systems

      Disclosed is a method that allows the interrupt request of an
IDE hardfile to be shared with another device (e.g., SCSI hardfile)
on interrupt level 14 within an IBM PS/2* system.

      The interrupt request (IRQ) of an IDE interface was designed to
be on a non-shared interrupt level.  According to PS/2 Micro Channel*
system architecture, all hardfile IRQs are shared on interrupt level
14.  In a Micro Channel computer system that supports both an IDE
hardfile and a SCSI hardfile, a problem arises.  The essence of the
problem is that because the IDE  interface IRQ was designed to be
non-sharing,  no IRQ "indicator bit" exists in any of the IDE status
registers.  In order for interrupt handling software to determine
which of two or more devices sharing an IRQ level is the requesting
device, an IRQ "indicator bit" or status bit is needed.  The Figure
shows a simple solution to provide the IRQ "indicator bit".

      To provide the IRQ "indicator bit" for the Micro Channel IDE
interface, bit 2 of port 92 was selected.  In previous systems bit 2

(port 92) was connected to a pin in the I/O controller chip called
SECURITY OVERRIDE.  SECURITY OVERRIDE is a signal that can be
mechanically jumpered to ground by a customer engineer to override
and reset the system password.  It sets port 92 bit 2 which is read
by POST during system power-up initialization.  In normal functional
operation...