Browse Prior Art Database

Partial Memory Bank Usage for Personal Computers

IP.com Disclosure Number: IPCOM000113027D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Haig, R: AUTHOR [+3]

Abstract

Described is a software implementation for personal computer users to provide a means of utilizing a bank of memory that is partially defective, thereby eliminating the need to replace an entire memory bank.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Partial Memory Bank Usage for Personal Computers

      Described is a software implementation for personal computer
users to provide a means of utilizing a bank of memory that is
partially defective, thereby eliminating the need to replace an
entire memory bank.

      A redirecting memory addressing method is used to allow the
continued usage of a defective memory bank.  The method redirects
addresses so as to bypass a defective memory block utilizing a
register array to control this capability.

      In prior art, if only one bit in a bank of memory became
defective, the entire bank had to be replaced, due to the direct
memory addressing requirements of the memory controllers.  For
example, the disk operating system (DOS) requires all system memories
to occupy a contiguous logical address space.  Memory controllers are
used to drive the processor address directly.  A defective portion of
a bank of memory could not be disabled without leaving a gap in the
address space.

      The concept described herein provides a means of bypassing the
defective area of memory so as to eliminate the need to replace the
entire memory bank.  The implementation relies on an indirect memory
addressing method to provide a set of programmable address
translation registers in the memory controller to translate the
processor's address into an appropriate memory address.  The
translation registers are organized in the form of an array which
represents the entire logical address space available for the system
memory.  Each register corresponds to a segment of address space,
while the contents of each register provides an address pointer to
the physical memory that will be accessed during a memory cycle
involved with this segment of address space.

      When the processor initiates a memory cycle, the memory
controller uses the high order of the processor's address bits as an
index to the register array.  These address bits select...