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Browse Prior Art Database

Data/Address Multiplex on Look-Through L2-Cache

IP.com Disclosure Number: IPCOM000113029D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Furuta, M: AUTHOR

Abstract

Disclosed is a method of multiplexing data and address on a look-through L2-cache. This L2-cache transfers data received from a CPU to a memory controller through CPU address bus when L2-cache write-miss occurs. And the L2-cache transfers data received from the memory controller through the CPU address bus to the CPU data bus when L2-cache read-miss occurs. The L2-cache or the memory controller drives the CPU address bus high-impedance during the above data transfer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Data/Address Multiplex on Look-Through L2-Cache

      Disclosed is a method of multiplexing data and address on a
look-through L2-cache.  This L2-cache transfers data received from a
CPU to a memory controller through CPU address bus when L2-cache
write-miss occurs.  And the L2-cache transfers data received from the
memory controller through the CPU address bus to the CPU data bus
when L2-cache read-miss occurs.  The L2-cache or the memory
controller drives the CPU address bus high-impedance during the above
data transfer.

      The Figure shows bus and control signals with a CPU, a
look-through L2-cache and a memory controller.  Data bus and address
bus work normally during the L2-cache hit operation.  When L2-cache
miss occurs, the L2-cache activate Cache Miss signal.  Then the
memory controller activates Data Req signal during write operation or
activates Data Ready signal during read operation.  High-Z Req signal
drives the CPU address bus high-impedance.

      This method can change data bus width, e.g. from 64-bit width
to 32-bit width, when the L2-cache transfers data to the CPU address
bus.  This method reduces I/O pins of memory controller.  Then the
memory controller package becomes small.