Browse Prior Art Database

Error Reporting on Fast Release PIO Stores

IP.com Disclosure Number: IPCOM000113036D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+2]

Abstract

Disclosed is a method for reporting errors during fast release PIO Store operations without impacting performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 85% of the total text.

Error Reporting on Fast Release PIO Stores

      Disclosed is a method for reporting errors during fast release
PIO Store operations without impacting performance.

      There are two types of PIO Store operations that are supported
on the RS/6000* System I/O (SIO) Bus, one for normal PIO Store
performance and one for high performance graphics applications.  The
SIO bus protocol requires that only one PIO store is outstanding at
any given time to insure precise interrupts on errors for normal PIO
Stores.  The I/O controller uses the SIO bus LOCK/BUSY protocol to
report errors to the Storage Control Unit (SCU) which in turn
generates a Data Storage Interrupt to the processor.  The fast
release PIO Store allows the I/O controller to accept multiple PIO
stores back to back by not requiring the I/O controller to report
errors to obtain better performance for graphics applications.  In
fact, the SCU ignores SIO LOCK during fast release PIO stores.

      This method provides error reporting for fast release PIO
Stores without sacrificing the performance of the fast release PIO
Stores.  An Error Log Register is added to the I/O controller with
different bit settings indicating different types of errors.  Also
added to the I/O controller is an Interrupt Vector Register which
software initializes during IPL with an External Interrupt Vector.
When the I/O controller detects an error during a fast release PIO
store operation, it sets the corresponding bit in the Er...