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Browse Prior Art Database

Software Simulation of the Asynchronous Communications Port

IP.com Disclosure Number: IPCOM000113037D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Mathew, G: AUTHOR

Abstract

Described is a software simulation implementation of the asynchronous communications port for use during Personal Computer (PC) testing. The implementation provides interaction to video subsystems, or information panels, providing test information so as to eliminate extensive hardware.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Software Simulation of the Asynchronous Communications Port

      Described is a software simulation implementation of the
asynchronous communications port for use during Personal Computer
(PC) testing.  The implementation provides interaction to video
subsystems, or information panels, providing test information so as
to eliminate extensive hardware.

      Typically, Power-On System Test (POST) operations are performed
to test the various functions of a PC.  The Central Processing Unit
(CPU) is generally tested first, followed by a test of the CPU/cache
circuitry.  When the CPU/cache circuitry is verified, then the base
circuit card is tested, followed by the channel, memory bus and
planar functions.  Since the CPU/cache is tested first, there are no
signals passed between the CPU/cache complex and the planar.
Isolating the CPU/cache complex from the rest of the system restricts
error codes and other diagnostic information from being displayed on
a video monitor, or an information panel.  The concept described
herein provides a method whereby the CPU/cache complex can directly
communicate to a video display through the use of a software
simulator.  This is done by displaying vital error codes and
checkpoints to an ASCII terminal.  It is primarily used during POST
development and manufacturing testing operations.

      In the CPU/cache complex, an output pin is provided as a
transmit output that is controllable through a local register on the
CPU/cache complex.  Setting the transmit bit of the local register to
a zero will condition the transmit pin to zero volts.  By toggling
the transmit bit, software is able to produce a signal capable of
transmitting serial data to an ASCII terminal.  The ASCII terminal is
attached to the CPU/cache complex through a serial cable with a
modified connector.  The modified connector allows easy attachment to
the CPU/cache complex and ties the circuit card's transmit pin to the
transmit wire of the serial cable.

      Serial data is sent from the CPU/cache complex to an ASCII
terminal in asynchronous data character format, as shown in Fig. 1.
The idle state is called the mark state at 0 volts.  To start
asynchronous communications,...