Browse Prior Art Database

Clock Mode for Reading Memory

IP.com Disclosure Number: IPCOM000113056D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+4]

Abstract

Disclosed is a method to eliminate wait states in an interleave-mode, 16-byte packet memory access. Memory access control signals for a memory cycle are issued on the cycle prior to the actual memory access.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Clock Mode for Reading Memory

      Disclosed is a method to eliminate wait states in an
interleave-mode, 16-byte packet memory access.  Memory access control
signals for a memory cycle are issued on the cycle prior to the
actual memory access.

      For accessing memory, the Intel 80486 microprocessor implements
a burst packet protocol, which can request four consecutive 32-bit
packets of data.  With this protocol, the time required to enable
data from the latches becomes critical.  The data buffers have to
multiplex or change the data within one clock cycle, while
maintaining setup and hold time requirements.  The ideal situation
for this burst packet protocol is to return data to the processor
with each clock pulse.

      The various signals associated with reading four double words,
indicated as A, B, C, and D, with a clock cycle occurring at 33 MHz
are shown in Fig. 1.  At this frequency, a clock cycle is 30 ns.
However, the clock to latch control time is 15 ns, the latch enable
time is 10 ns, and the data setup time at the processor is 5 ns, so a
margin of only 3 ns remains in the data setup for the second and
fourth double words.

      When the frequency of operation is increased to 40 MHz, the
data setup time to the processor is not met by this type of
operation, since the clock cycle time is decreased to 25 ns without
changing the other parameters, causing this setup time to be missed
by 2 ns.  Therefore, a wait state is typically added, reducing system
performance as shown in Fig. 2.

      While the wait state could be removed by using faster d...