Browse Prior Art Database

Resonant Power Supply for Hot-Clock Reversible Low Power Computing

IP.com Disclosure Number: IPCOM000113074D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 177K

Publishing Venue

IBM

Related People

Hartstein, A: AUTHOR

Abstract

The idea of using a Hot-Clock technique in conjunction with reversible computing in order to reduce the energy dissipation used during computation, has been discussed recently [1-3]. The technique has great merit, but in general it shifts the problem of energy dissipation, away from the logic circuitry performing the calculations, to the power supply. The present disclosure is a power supply capable of powering properly designed logic circuits while dissipating arbitrarily small amounts of energy in both the logic circuits and the power supply.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 32% of the total text.

Resonant Power Supply for Hot-Clock Reversible Low Power Computing

      The idea of using a Hot-Clock technique in conjunction with
reversible computing in order to reduce the energy dissipation used
during computation, has been discussed recently [1-3].  The technique
has great merit, but in general it shifts the problem of energy
dissipation, away from the logic circuitry performing the
calculations, to the power supply.  The present disclosure is a power
supply capable of powering properly designed logic circuits while
dissipating arbitrarily small amounts of energy in both the logic
circuits and the power supply.

      The essential problem in ultra-low power computing is to
provide a logic circuit/power supply combination in which power can
be provided to the logic circuitry during computation and then
reabsorbed by the power supply when it is not needed.  If this is not
done carefully, the energy will be dissipated as heat in either the
logic circuitry or the power supply.  Logic circuitry, which is
capable of functioning in this fashion, has been discussed.  However,
the second half of the problem, the matching power supply, has been
neglected.

      One typically chooses CMOS technology for low energy
semiconductor logic and memory functions.  That is because CMOS
circuitry has negligible power requirements while static, and only
dissipates energy during a switching operation.  This dynamic power
requirement typically involves charging gate and interconnect
capacitances during the switching operations.

      Fig. 1 shows a CMOS inverter, a generic circuit for the
technology.  During operation of the circuit, the load capacitance,
C, must be alternately charged and discharged through the p and n
channel MOSFET transistors (TP and TN) in the circuit.  Other logic
functions will have a similar requirement.  During these repeated
chargings and dischargings power is dissipated in the transistors due
to their finite resistance.  If the power supply voltage is V, the
energy lost in the charging cycle is frac12 C V sup 2, independent of
the resistance of the p-channel transistor.  During the discharge
cycle the energy stored in the capacitance, frac12 C V sup 2, is
dissipated in the n-channel transistor.

      The dissipated energy during the charging cycle is proportional
to the voltage drop across the transistor during the charging
process.  During the start of the charging process, the full power
supply voltage, V, is dropped across the transistor, and a large
dissipation occurs.  As the charging proceeds, the dissipation rate
decreases.  If one can insure that  only a negligibly small voltage
appears across the transistor at all times, then the energy
dissipation will become negligibly small.  This can be done if the
power supply voltage is slowly ramped up from 0 to the voltage V.
The ramp speed needs to be much smaller than the RC time constant,
which governs the normal charging of the capacita...