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Electromagnetic Interference Reduction through Time Distribution of Clock Signals

IP.com Disclosure Number: IPCOM000113080D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Donaldson, JE: AUTHOR [+3]

Abstract

A method for reducing Electromagnetic Interference (EMI) emissions is disclosed. Time distribution of digital gate switching and farfield cancellation is used.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Electromagnetic Interference Reduction through Time Distribution
of Clock Signals

      A method for reducing Electromagnetic Interference (EMI)
emissions is disclosed.  Time distribution of digital gate switching
and farfield cancellation is used.

      A solution to reducing the EMI radiated emissions and the
voltage/ground noise can be accomplished by reducing the simultaneous
digital switching.  This can be accomplished by spreading the digital
gate switching over time instead of having all the logic gates
switching at the same time.

      A significant portion of the radiated emissions is caused by
the common mode current flowing on the external power and Small

Computer System Interface (SCSI) cables.  To reduce the EMI radiated
emissions, the common mode currents on the external cables must be
reduced.  To reduce the common mode currents on the external cables,
the common mode voltages in the electronics ground and voltage planes
must be reduced.  To do this, the differential mode currents must be
reduced and the distance the differential currents must travel must
be reduced.

      By spreading the digital switching over time, the peak current
required is reduced since the digital switching does not occur at one
time.  This also reduces the instantaneous charge required during
switching (Fig. 1).

      The charge required for switching is stored in the decoupling
capacitors, the distributed capacitance in the voltage/ground planes
and the bulk capacitance on the printed circuit board.  More
capacitance is required to provide a larger instantaneous charge.
For larger charge requirement, the charge is supplied by capacitance
farther from where the switching is taking place.  This causes the
currents to travel a longer distance which in turn causes larger
common mode voltages to occur in the voltage and ground planes due to
the increased impedances.

      In addition to reducing the common mode currents on the cables,
there is some differential mode noise reductions caused by having the
clocks 180 degrees out-of-phase.  By having the clocks out-of-phase,
the far field EMI emissions are reduced due to cancellation effects
of adding the two clocks together during EMI radiated measurements.

      This can be accomplished by using gate delays and operating
clock drivers out-of-phase with each other.  To do this, we used a
module which has several logic gates to propagate the clock signal to
several other modules.  The output of each of the logic gates is
connected to one of the inputs of the next gate and the other inputs
are connected to +5 voltage.  See Fig. 2 for a graphical
representation of this clock driver circuit.  By cascading the
outputs of the clock, each subsequent clock output is delayed by...