Browse Prior Art Database

Improved Graphic Image Bitmap Structure for Personal Computers

IP.com Disclosure Number: IPCOM000113081D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 8 page(s) / 302K

Publishing Venue

IBM

Related People

Lam, SH: AUTHOR [+2]

Abstract

Described is an architectural implementation designed to improve the graphic image bitmap structure and controlling apparatus and to enable horizontal, vertical, and quadrangle area accesses, for use in Personal Computers (PCs). The implementation relates to the graphic image buffer, or bitmap, structure and controlling logic dedicated for use by a graphic controller bus master to the bitmap.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 30% of the total text.

Improved Graphic Image Bitmap Structure for Personal Computers

      Described is an architectural implementation designed to
improve the graphic image bitmap structure and controlling apparatus
and to enable horizontal, vertical, and quadrangle area accesses, for
use in Personal Computers (PCs).  The implementation relates to the
graphic image buffer, or bitmap, structure and controlling logic
dedicated for use by a graphic controller bus master to the bitmap.

      In the bitmap structure, bits of image data are allocated to
plural memory modules in the form of memory chips, or memory macros.
The number of plural memory modules is the same as the band width of
the system data bus.  The bitmap is used to enable any of the
horizontal linear, vertical linear, or quadrangle area accesses,
starting from any pixel address in the bitmap.  The bitmap performs
this function in a single DWORD, or WORD data access, referring the
preset values to peripheral latches to indicate which of the three
accessing modes are selected.  Also, it determines which pixel
boundary offset the bus master will start the access.

      When the bit master attempts to access the bitmap, the bus
address from the bus master is converted to the appropriate address
in each memory module as controlled by the controlling logic.  At the
same time, each memory module selects an appropriate data line from
all the data bus lines as set by the preset values.  Therefore, only
a single access by the bus master can access any of the horizontal
linear, vertical linear, or quadrangle areas starting from any pixel
boundary location in the bitmap.

      Generally, for any kind of image handling subsystem, such as
graphic display adapters, page printer controllers, etc., it is
mandatory that the subsystem be equipped with an All Point
Addressable (APA) graphic image buffer to be used as a storage for
the final pixel image output device.  The image buffer is typically
known as the bitmap.

      The bus master of each subsystem attempts to read/write pixel
image data from/to any area of the bitmap in order to generate, or
modify, the final image to the output.  This accessing by the bus
master is usually executed by using the full bandwidth of the data
bus connected from the bus master through the bit map memories.
Therefore, a plural number of pixels are accessed in a single access
by the bus master, simultaneously.

      In some cases, it is effective for the bus master to access the
bitmap linearly along the X direction sequentially (horizontal
linear).  In other cases, it is effective to access linearly along
the Y direction sequentially (vertical linear).  For quadrangle area
accesses, a single read/write might be the most effective way to
generate an image on the bitmap.  Much of the accessing depends on
how each memory element in the memory modules, which comprise the
bitmap, is corresponding to each pixel of the bitmap and which of the
three acc...