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High Density Parallel to Serial Shift Register

IP.com Disclosure Number: IPCOM000113082D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Busch, RE: AUTHOR [+3]

Abstract

Dynamic Random Access Memory (DRAM) chip designs have incoporated programmable fuses to facilitate tracking chips through fabrication and test, as well as in inventory. A technique to electrically read fuse states using a parallel to serial shift register conversion technique is described here, allowing fuse states to be read through a single output pin from the chip, and requiring fewer signals to operate the circut than in conventional decode schemes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Density Parallel to Serial Shift Register

      Dynamic Random Access Memory (DRAM) chip designs have
incoporated programmable fuses to facilitate tracking chips through
fabrication and test, as well as in inventory.  A technique to
electrically read fuse states using a parallel to serial shift
register conversion technique is described here, allowing fuse states
to be read through a single output pin from the chip, and requiring
fewer signals to operate the circut than in conventional decode
schemes.

      Fig. 1 is the shift register block diagram.  It comprises two
main sections, or blocks.  The first block represents the shift
register that samples multiples parallel inputs, and has a single
serial output labeled SRSER.  The second block generates the clock
pulses, and controls the shift register stages in the first block.
Clock inputs are RASP, CASP, and TEST MODE SELECT.  RASP and CASP are
buffered versions of the DRAM RAS and CAS inputs.  TEST MODE SELECT
is a signal generated to turn on the shift register circuts, which
are powered off when not in use.  Outputs from the shift register
clocks are POWER, P1, P2, P2N, and REST, as wekk as SERIAL OUTPUT:  G
PIN.  POWER provides the first bit launched into the shift register
stages, and is at a logic high level for only this first transition.
Thereafter P1 switches low, and remains low for the duration of the
fuse reading operation.  P1 and P2 are the clock signals which cause
the first bit generated by P1 to be transferred from stage to stage
through the shift register.  The RSET signal insures that at power up
time, the shift register stages are all initialized to their reset
state.  RSET signal is at a high state when POWER signal first rises,
and returns to a low logic state at the first shift into the shift
register stages.  The SERIAL OUTPUT can go to any signal pin in the
DRAM.  It is shown here going to the G pin.

      Fig. 2 shows the schematic of the shift register clocks.  The
initial voatage conditions on the circuit are with the TEST MODE
SELECT input at a high logic level, which keeps all the shift
registers in a standby state.  Nodes POWER, RSET, P1, P2, and P2N are
all of the shift register stages are powered off.  Invrters I1
through I10, I13 through I17 gates A1, A3, A4, A5, and O1 are powered
by the normal chip voltage buss, which is not shown as a separate
input.  All other circuts are powered by POWER node.  Refer to Fig. 3
for the timing diagram for the following description.

      The shift register circuits are activated when the TEST MODE
SELECT input switches to a low logic level.  This chip operation
occurs during a Test Mode chip cycle, which is detected and pulls
node TEST MODE SELECT to ground.  Nodes TEST MODE and RASP remain
logic low and high, respectively, for the duration of the shift
register operations. ...