Browse Prior Art Database

Buffer Management Techniques for Enhanced Data Integrity

IP.com Disclosure Number: IPCOM000113119D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Gramann, PA: AUTHOR [+6]

Abstract

Three techniques (redundancy code invalidation, segment staggering, and post-transfer address verification) are disclosed that significantly reduce the probability of transferring incorrect data.

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Buffer Management Techniques for Enhanced Data Integrity

      Three techniques (redundancy code invalidation, segment
staggering, and post-transfer address verification) are disclosed
that significantly reduce the probability of transferring incorrect
data.

      Three techniques significantly increase the probability of
detecting errors in blocks of data stored in a RAM that may not be
detected by the straight forward use of a redundancy code.

1.  Redundancy Code Invalidation

          Prior to storing a new block of data in the RAM, the old
    data at that location is modified in order to invalidate the
    redundancy code of the old block.  If the new block is then
    stored at an incorrect location and the old block is retrieved,
    the redundancy check of the old block will fail, signaling an
    error.

2.  Segment Staggering

          The absolute starting address of the segments (groups of
    blocks) are defined so that a single bit address failure cannot
    cause the hardware to access data at the exact start of a
    different segment.  For example, segments starting at addresses
    0x0000, 0x1001, 0x2002, require at least a two bit address
    failure in order to access the exact start of a different
    segment.  Using this technique, a block of data accessed from the
    wrong segment (due to a single bit address failure or segment
    selection hardware failure) will span two blocks (...