Browse Prior Art Database

High Speed Current Switch for Digital to Analog Converter

IP.com Disclosure Number: IPCOM000113126D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Goetschel, CJ: AUTHOR [+8]

Abstract

Disclosed is a circuit topology for high-speed, low-glitch energy current switch that can be used to implement high performance Digital to Analog Converters (DAC).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Speed Current Switch for Digital to Analog Converter

      Disclosed is a circuit topology for high-speed, low-glitch
energy current switch that can be used to implement high performance
Digital to Analog Converters (DAC).

      The circuit shown in the Figure was used to implement the
current switch.  The fast switching speed and low-glitch energy was
accomplished with two key circuit techniques.  First, by keeping the
MOSFETs that steer the current to the output (T3,T5,T8 and T10)
biased at a point where they turn on and off fast, the switch will
respond quickly to changes of the digital inputs.  Secondly, the
speed of the current switch is greatly enhanced by keeping the LSB
(least significant bit) reference currents provided by FETs T1 and T7
always flowing into a constant voltage node (NET2 and NET5) such that
these currents don't have to charge and discharge parasitic
capacitance when they are switched to the output.  The circuit
operation is detailed below.

      Binary weighted groups of the current switch shown in the
Figure are tied together with a common S0 (select) pin that is driven
by a digital control line.  The I0 and D0 pins of the switch control
the direction of current flow at the output pin (10).  The N0 and P0
pins are driven from analog current mirror references that set the
amount of output current that can be sourced or sunk by the current
switch.  This reference current can be programmable to allow the
full-scale output range of the DAC to vary.  The V0 pin is biased up
with a half power supply reference voltage that is used to bias
devices internal to the current switch.  The truth table for the
current switch is shown in the following table:

      This circuit receives a PFET and NFET bias voltage from pins P0
and N0 respectively.   FETs T1 and T7 are biased up as current
sources each carrying a LSB of current.  This current is steered
either to the outp...