Browse Prior Art Database

Multiple Mode Selector for Input/Output Circuitry

IP.com Disclosure Number: IPCOM000113147D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 90K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+4]

Abstract

Described is a hardware circuit implementation that increases the level of functionality of an integrated digital chip by incorporating an integrated multiple mode selector, with storage capability, in the Input/Output (I/O) cells associated with the chip's external interfaces.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple Mode Selector for Input/Output Circuitry

      Described is a hardware circuit implementation that increases
the level of functionality of an integrated digital chip by
incorporating an integrated multiple mode selector, with storage
capability, in the Input/Output (I/O) cells associated with the
chip's external interfaces.

      The implementation allows signal multiplexing for I/O and
bi-directional signals, through programmable control signals, and is
designed to increase the effectiveness of available signal pins on a
packaged chip.  Described are three circuit implementations for
applying the multiple mode selector for input, output, and
bi-directional signal pins.

      In prior art, circuit chips, which contain a Central Processing
Unit (CPU) and associated controller units, had multiple bus
implementations on a single chip package.  Physical limitations of
certain forms of integrated chip packages placed an upper-bound limit
on the pin count.  In high performance applications, large numbers of
simultaneously switching drivers occurred during a single clock
cycle.  When high levels of integration occurred on a single chip,
excessive switching activity was created within the logic core of the
chip.  This in turn caused electrical effects that required a means
of reducing the electrical noise within the chip.

      In prior art, the internally created electrical noise was
reduced by increasing the number of power pins, including ground
pins, required at the first level of packaging.  This effectively
reduced the number of signal pins available for functional
applications and in turn required some means of increasing the level
of functionality in a packaged chip where the number of available
signal pins was limited.

      The concept described herein provides a means of increasing the
level of functionality of an integrated digital chip by incorporating
an integrated multiple mode selector, with storage capability, in the
I/O cells associated with the external interfaces of the chip, while
minimizing the impact of wiring congestion and chip density.  The
concept allows signal multiplexing for the I/O and bi-direct...