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Circuit Optimization of Error Correction and Control/Parity Data Path

IP.com Disclosure Number: IPCOM000113156D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Bishop, RH: AUTHOR

Abstract

Described is a hardware implementation that optimizes Error Correction and Control (ECC)/parity circuitry, as used in Direct Memory Access (DMA) control circuitry in Personal Computers (PCs). The implementation is accomplished by sharing common logic paths with data selected through multiplexors and held by means of latches.

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Circuit Optimization of Error Correction and Control/Parity Data Path

      Described is a hardware implementation that optimizes Error
Correction and Control (ECC)/parity circuitry, as used in Direct
Memory Access (DMA) control circuitry in Personal Computers (PCs).
The implementation is accomplished by sharing common logic paths with
data selected through multiplexors and held by means of latches.

      The ECC/parity circuitry in a memory controller typically
involves large amounts of circuitry.  The concept described herein
reduces the number of gates used for ECC/Parity by sharing the same
exclusive-or (XOR) tree for reads, such as syndrome bits; writes,
such as check bits; and read-modify-writes, such as syndrome and
check bits.  The operation is performed while maintaining acceptable
system performance levels and full functionality.  The same XOR tree
is also used to generate and check parity, if parity mode is selected
rather than ECC mode.

      The Figure shows a block diagram of the optimization circuit.
During a read cycle, memory_data_in passes through multiplexor (MUX)
10 where it is latched to provide isolation from memory.  The data
then passes through MUX 11 and enters XOR tree 12 where syndrome
check and parity bits are generated.  For data in an ECC-type memory
system, the syndrome bits are decoded at decoder 13 where the data
bit in error gets corrected and sent to MUX 14.  The corrected data
from XOR 14 goes to the system by way of MUXs...