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Using Good Machine Characterization for Scan Diagnostics

IP.com Disclosure Number: IPCOM000113177D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 107K

Publishing Venue

IBM

Related People

Carrier, DW: AUTHOR [+4]

Abstract

Disclosed is an algorithm for using good machine characterization to improve diagnostic calls for Level Sensitive Scan Design (LSSD) based circuits which fail scan path testing. Due to occasional limitations in design for diagnosability, latches with pseudo-random pattern resistant or tied input data ports may cause incorrect diagnoses for defects in a scan chain. The same applies for scan-only latches, which have no data ports. These latches can be identified by using good machine characterization, and the fault equivalence class associated with many of these defects can be adjusted accordingly, thereby giving an accurate repair call.

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Using Good Machine Characterization for Scan Diagnostics

      Disclosed is an algorithm for using good machine
characterization to improve diagnostic calls for Level Sensitive Scan
Design (LSSD) based circuits which fail scan path testing.  Due to
occasional limitations in design for diagnosability, latches with
pseudo-random pattern resistant or tied input data ports may cause
incorrect diagnoses for defects in a scan chain.  The same applies
for scan-only latches, which have no data ports.  These latches can
be identified by using good machine characterization, and the fault
equivalence class associated with many of these defects can be
adjusted accordingly, thereby giving an accurate repair call.

      The disclosed algorithm is used to improve the accuracy of
defect detection for LSSD-based chips and/or multi-chip modules that
fail scan path testing on scan rings with fixed input or
pseudo-random pattern resistant data ports (hereafter referred to as
simply "pattern resistant SRL's").  Upon failing scan path testing,
the lateral insertion algorithm must be applied to gate pseudo-random
data into the capture latch of every Shift Register Latch (SRL) in
the failing self-test channel.  The channel is then unloaded, and the
data is examined to locate the point at which pseudo-random data
stops and stuck data begins.  Multiple patterns are used, of course,
to decrease the probablility of the latch immediately below the
defect location coincidentally matching the defect symptom data.

      However, if the latch(es) immediately below a defect have
pattern resistant inputs and they coincidentally match the defect
symptom data, then the symptom location will be mis-identified for
all patterns.  This will lead to incorrect failure analysis data,
and, in a multi-chip channel, could cause an altogether incorrect
repair call.

      With this algorithm, all of the patterns to be used for lateral
insertion are first simulated.  This good machine characterization
data is then used to identify the pattern resistant SRL's.  The
simulation is performed once, and all of the data is stored.  When
lateral insertion is subsequently performed on a failing part, the
symptom SRL is then cross-referenced with the list of pattern
resistant SRL's to determine if the symptom location has been
corrupted by pattern resistant data.  If this does occur, then the
SRL above the symptom location is cross-referenced with the pattern
...