Browse Prior Art Database

Planarity Layout Design for VLSI Chip Manufacturing

IP.com Disclosure Number: IPCOM000113185D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Cronin III, DR: AUTHOR [+2]

Abstract

Disclosed is a method of updating every metal layer on a VLSI chip to improve the decoupling of the power supply circuits. At a point when other design processes have been completed, all metal layers used to provide power to each circuit on the chip are enlarged. This point in the design process may be defined, for example, by the completion of a clean Design Rule Check (DRC).

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Planarity Layout Design for VLSI Chip Manufacturing

      Disclosed is a method of updating every metal layer on a VLSI
chip to improve the decoupling of the power supply circuits.  At a
point when other design processes have been completed, all metal
layers used to provide power to each circuit on the chip are
enlarged.  This point in the design process may be defined, for
example, by the completion of a clean Design Rule Check (DRC).

      The enlargement of these layers may be provided, for example,
by a program written to widen each power bus, using up all adjacent
empty areas without shorting adjacent signal lines.  This process
would be applied to all metal layers for both VCC and ground bussing.
While an obvious concern is the added capacitive loading on signal
lines, the mutual capacitance is typically negligible.  A final DRC
is run after the busses are enlarged, before manufacturing the chip.

      This method provides additional capacitance at the power supply
pins due to the additional metal, increasing the decoupling of the
power supply from any high-frequency noise.  Also, the noise
decoupling of signal lines is improved, since signal lines are
increasingly shielded by power bussing planes.  Power supply
distribution is improved by eliminating unforeseen electromigration
or DC problems.  Furthermore, the metallurgy is improved at all
levels.  Since all metal layers have approximately the same amount of
metal, the planarity is improved, an...