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Compact, High Performance I2L Structure

IP.com Disclosure Number: IPCOM000113190D
Original Publication Date: 1994-Jul-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 98K

Publishing Venue

IBM

Related People

Patton, GL: AUTHOR [+2]

Abstract

Disclosed is a process for merging the NPN and PNP transistors in the Symmetrical Profile Epitaxial Complementary TRAnsistor (SPECTRA). structure to produce a compact Integrated-Injection Logic (I2L) circuit with high performance NPN and PNP transistors.

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Compact, High Performance I2L Structure

      Disclosed is a process for merging the NPN and PNP transistors
in the Symmetrical Profile Epitaxial Complementary TRAnsistor
(SPECTRA).  structure to produce a compact Integrated-Injection Logic
(I2L) circuit with high performance NPN and PNP transistors.

      I2L, known also as Merged-Transistor Logic (MTL), offers
significantly higher density, lower power dissipation, and better
wiring efficiency than Emitter Coupled Logic (ECL).  However, the
speed of I2L circuits has traditionally lagged behind that of ECL
because of the poor performance of the upward-operated NPN
transistors and the lateral PNP transistors.

      High performance NPN and PNP transistors can be obtained on the
same wafer using SPECTRA &R1..  In this approach, advanced epitaxial
techniques (i.e., molecular beam epitaxy) are used to obtain a
vertical profile which is symmetric around the NPN base-collector
junction.  This allows the junction to be used simultaneously by a
high performance vertical NPN transistor operating in the upward
direction and by a high performance PNP transistor operating in the
downward direction, as shown in Fig. 1.

      The NPN and PNP transistors in the SPECTRA structure can be
merged to produce an extremely compact, high speed I2L circuit.  Fig.
2 shows a cross section of this approach in its simplest form.  The
collector of the PNP transistor is merged with the base of the NPN
transistor to shrink the cell size and eliminate the need for deep
trenches and P+ reach-thru's.  If the deep trenches are left in, the
compact I2L structure could be merged with ECL logic to obtain high
speeds, high densities, and low power consumption on the same chip.

      Further improvements in performance can be realized by reducing
minority carrier charge storage in regions of the P layer which are
extrinsic to the collectors of the NPN transistor and by decreasing
the collector resistance of the PNP transistor.  This can be
accomplished by using the RIE etch of the N SiGe layer in the
extrinsic base region to also remove the P SiGe layer in that
regions, as shown in Fig. 3.  As a result, the extrinsic base-emitter
junction is changed f...